The paper introduces a reinforcement‑learning framework that automatically discovers compact parametrized quantum circuits for modeling power GaN HEMTs and logic nanowire FETs. Using a graph neural network policy trained with proximal policy optimization, the method optimizes circuit architectures based on leave‑one‑group‑out cross‑validation error, achieving the lowest mean absolute error across 11 targets compared to six classical baselines. The results show significant reductions in error and variability for key device metrics (Ioff, VTH, SS) on both HEMT and NWFET datasets, demonstrating the viability of RL‑selected quantum circuits as compact, physically consistent surrogates without explicit physical constraints.
By Rushat Rai, Yun-Yuan Wang, Autsada Kakaen, Pei-Jie Chang, Doan Viet Nguyen, Yuan-Chieh Chiu, Doldet Tantraviwat, Niall Tumilty, Simon See, Wen-Jay Lee, Tai-Yue Li, Nan-Yow Chen, Tian-Li Wu
arXiv:2606. 24046v1 Announce Type: cross Abstract: This work presents a machine learning framework that leverages an autoencoder (AE) for the efficient modeling of FinFET.
By Amit Sarkar Suman Sau, Swagata Mandal
arXiv:2507.05134v2 Announce Type: replace
Abstract: We present a deep learning approach to extract physical parameters (e.g., mobility, Schottky contact barrier height, defect profiles) of two-dimens...
By Robert K. A. Bennett, Jan-Lucas Uslu, Harmon F. Gault, Asir Intisar Khan, Lauren Hoang, Tara Pe\~na, Kathryn Neilson, Young Suh Song, Zhepeng Zhang, Andrew J. Mannix, Eric Pop
The paper introduces a physics‑informed graph attention network that directly operates on the tetrahedral mesh used in TCAD simulations of FinFET devices. By predicting electrostatic potential and quasi‑Fermi levels at every mesh node and training with both data loss and finite‑volume current‑continuity residuals, the surrogate retains the underlying carrier‑transport physics while achieving size generalization. Benchmarks against Sentaurus Device show sub‑volt RMSE for the drift‑diffusion fields and a per‑design throughput that is orders of magnitude faster, enabling rapid Pareto‑front exploration of large multi‑fin arrays that would otherwise be prohibitively slow to simulate.
By Leonid Popryho, Ayoub Sadeghi, Inna Partin-Vaisband
arXiv:2609.07046v1 Announce Type: new
Abstract: AI has revolutionized various engineering domains, but its impact on semiconductor device design and defect discovery is still limited, due to limited...
By Hiu Yung Wong
arXiv:2607. 05187v1 Announce Type: new Abstract: As CMOS technology scales into the deep nanometer regime, digital circuit reliability is increasingly threatened by the combined stochastic effects of Bias Temperature Instability (BTI) and Process Variation (PV).
By Arash Esshaghi, Siavash Es'haghi, Gholamreza Shahabadi, Alireza Moradi
arXiv:2609.13200v1 Announce Type: cross
Abstract: Compact transistor models are the mathematical backbone of circuit simulation. However, at advanced nodes such as 3nm, transport physics becomes too...
By Pranavanath Balamurali, Prathamesh Dinesh Joshi, Raj Abhijit Dandekar, Rajat Dandekar, Sreedath Panat
arXiv:2608. 08048v1 Announce Type: cross Abstract: This paper presents, for the first time in power systems literature to our knowledge, analytical tools to explain the training performance of machine learning surrogate models for power system dynamics.
By Petros Ellinas, Johanna Vorwerk, Spyros Chatzivasileiadis
arXiv:2608. 16080v1 Announce Type: new Abstract: Thermal-aware optimization of multi-die 3D integrated circuits evaluates many designs, each a costly heat-equation solve.
By Xinling Yu, Yixing Li, Ziyue Liu, Xin Ai, Zhiyu Zeng, Hai Li, Zheng Zhang
As CMOS technology scales into the deep nanometer regime, digital circuit reliability is increasingly threatened by the combined stochastic effects of Bias Temperature Instability (BTI) and Process Variation (PV). Traditional reliability analysis methods, which rely on computationally intensive simulations or extensive lookup tables, fail to scale efficiently for large designs, creating a critical bottleneck in design space exploration.
arXiv:2504. 03711v2 Announce Type: replace-cross Abstract: Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications.
By Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Yuchao Wu, Yuzhe Ma, Zhiyao Xie
arXiv:2508. 16403v3 Announce Type: replace Abstract: Accurately predicting the performance of active radio frequency (RF) circuits is essential for modern wireless systems but remains challenging due to highly nonlinear behavior and the high computational cost of traditional simulation tools.
By Anahita Asadi, Leonid Popryho, Inna Partin-Vaisband