arXiv:2504. 03711v2 Announce Type: replace-cross Abstract: Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications.
arXiv:2603. 09161v2 Announce Type: replace-cross Abstract: Learning effective netlist representations is fundamentally constrained by the scarcity of labeled datasets, as real designs are protected by Intellectual Property (IP) and costly to annotate.
arXiv:2609.36752v1 Announce Type: new Abstract: Circuit design is a complex and iterative process that requires expertise in electronic engineering. It involves selecting components while meeting per...
Recent advances in Artificial Intelligence (AI) have revolutionized Electronic Design Automation (EDA), particularly through Large Language Models (LLMs) for circuit design tasks. However, their application to analog and mixed-signal domains remains limited by the lack of machine-readable representations of existing circuit design knowledge.
arXiv:2607. 01609v1 Announce Type: new Abstract: Recent advances in Artificial Intelligence (AI) have revolutionized Electronic Design Automation (EDA), particularly through Large Language Models (LLMs) for circuit design tasks.
arXiv:2608. 13472v1 Announce Type: cross Abstract: Analog circuit design is a time-consuming, iterative process in a nonlinear and high-dimensional design space that relies heavily on expert intuition.
ReDIL-GNN is a framework for resynthesis domain‑incremental learning in circuit graph neural networks. It adapts a fixed prediction or representation head as new synthesis styles appear and evaluates retention across all previously seen domains. The method introduces the Resynthesis Adaptability Index (RAI), a pre‑adaptation score that combines adaptation need, source‑equivalence recoverability, structural coverage, and update compatibility to decide whether to adapt, reuse, or defer updates.
arXiv:2609.07046v1 Announce Type: new Abstract: AI has revolutionized various engineering domains, but its impact on semiconductor device design and defect discovery is still limited, due to limited...
arXiv:2606. 16939v1 Announce Type: cross Abstract: A prominent research direction in mechanistic interpretability is learning sparse circuits over LLM components to reveal how they jointly produce model behavior.
arXiv:2509. 21886v3 Announce Type: replace Abstract: Learning to compute, the ability to model the functional behavior of a circuit graph, is a fundamental challenge for graph representation learning.
arXiv:2608.28188v1 Announce Type: new Abstract: Circuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical...
arXiv:2603. 13092v2 Announce Type: replace Abstract: Yield Multi-Corner Analysis validates circuits across 25+ Process-Voltage-Temperature corners, resulting in a combinatorial simulation cost of $O(K \times N)$ where $K$ denotes corners and $N$ exceeds $10^4$ samples per corner.
arXiv:2508. 10409v3 Announce Type: replace-cross Abstract: This paper constructs a textual dataset for training large language models (LLMs) to learn analog circuit knowledge and customizes LLM training techniques.