TARGet is an open‑source, topology‑aware machine‑learning framework for modeling RF circuits. It uses S‑parameter representations of sub‑circuits and a fusion architecture that combines Graph Neural Networks with sub‑circuit connectivity‑aware networks, enabling learning across multiple topologies. Experiments show TARGet achieves sub‑1% prediction error, reduces training data needs by up to 35.5×, and improves accuracy by 9.7× over state‑of‑the‑art models, with zero‑shot transfer to unseen sub‑circuit topologies.
By Soroosh Noorzad, Sebastian Bodero, Morteza Fayazi
arXiv:2607. 23225v1 Announce Type: new Abstract: As chip manufacturing processes advance to deep submicron nodes, parasitic interconnect effects increasingly dominate the performance of analog and mixed-signal (AMS) circuits and often lead to costly layout iterations.
By Jiajun Zou, Jiawei Liu, Ao Liu, Junnong Tian, Yibin Zhang, Chengjie Liu, Yuxi Wang, Shan Shen, Wenhua Gu, Jun Yang, Wenjian Yu
arXiv:2609.36752v1 Announce Type: new
Abstract: Circuit design is a complex and iterative process that requires expertise in electronic engineering. It involves selecting components while meeting per...
By Pasindu Dodampegama, Praveen Wijesinghe, Naveen Basnayake, Keshawa Jayasundara, Tharindu Bandaragoda
The paper introduces Multi-Channel Physics-Aware Random Walk Fingerprints (MC-PA-RWF), a lightweight graph-level representation that incorporates physical edge states into random-walk propagation for power grid graphs. By constructing multiple edge-weighted channels from domain-relevant attributes and concatenating channel-specific fingerprints, the method achieves high balanced accuracy on PowerGraph benchmarks, outperforming topology-only RWF and matching or surpassing several graph neural network baselines. Experiments on three benchmark systems show statistically significant improvements, with the node-edge extension reaching up to 99.32% balanced accuracy and boosting failure-class F1 scores by 1.60–5.84 percentage points.
By Adnan Anwar
arXiv:2509. 21886v3 Announce Type: replace Abstract: Learning to compute, the ability to model the functional behavior of a circuit graph, is a fundamental challenge for graph representation learning.
By Ziyang Zheng, Jiaying Zhu, Jingyi Zhou, Qiang Xu
arXiv:2507. 06849v3 Announce Type: replace-cross Abstract: Neural network (NN)-based Digital Predistortion (DPD) improves linearization for wideband radio frequency (RF) power amplifiers (PAs) but often increases the complexity of the digital back-end.
By Yizhuo Wu, Ang Li, Chang Gao
arXiv:2602. 01553v3 Announce Type: replace-cross Abstract: Link prediction is a core challenge in graph machine learning, demanding models that capture rich and complex topological dependencies.
By Quang Truong, Yu Song, Donald Loveland, Mingxuan Ju, Tong Zhao, Neil Shah, Jiliang Tang
arXiv:2603. 16565v2 Announce Type: replace-cross Abstract: This article presents a deep learning-driven inverse design methodology for Doherty power amplifiers (PA) with multi-port pixelated output combiner networks.
By Han Zhou, Haojie Chang, David Widen
ReDIL-GNN is a framework for resynthesis domain‑incremental learning in circuit graph neural networks. It adapts a fixed prediction or representation head as new synthesis styles appear and evaluates retention across all previously seen domains. The method introduces the Resynthesis Adaptability Index (RAI), a pre‑adaptation score that combines adaptation need, source‑equivalence recoverability, structural coverage, and update compatibility to decide whether to adapt, reuse, or defer updates.
By Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu
arXiv:2504. 03711v2 Announce Type: replace-cross Abstract: Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications.
By Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Yuchao Wu, Yuzhe Ma, Zhiyao Xie
K-TRAIL is a simulator-guided generative framework that uses diffusion-based layout generation combined with derivative-free ensemble Kalman guidance to design RF and electromagnetic circuits. It allows a black-box EM simulator to refine candidate layouts during generation, supporting synthesis from target S-parameter responses or direct RF performance constraints. Experiments on multi-layer RFIC structures demonstrate improved agreement with target responses and the ability to discover structurally distinct layouts that meet design requirements.
By Piyush Saha, Evan Newell, Hanna O'Leary, Arun Natarajan, Alireza Aghasi
The paper introduces a reinforcement‑learning framework that automatically discovers compact parametrized quantum circuits for modeling power GaN HEMTs and logic nanowire FETs. Using a graph neural network policy trained with proximal policy optimization, the method optimizes circuit architectures based on leave‑one‑group‑out cross‑validation error, achieving the lowest mean absolute error across 11 targets compared to six classical baselines. The results show significant reductions in error and variability for key device metrics (Ioff, VTH, SS) on both HEMT and NWFET datasets, demonstrating the viability of RL‑selected quantum circuits as compact, physically consistent surrogates without explicit physical constraints.
By Rushat Rai, Yun-Yuan Wang, Autsada Kakaen, Pei-Jie Chang, Doan Viet Nguyen, Yuan-Chieh Chiu, Doldet Tantraviwat, Niall Tumilty, Simon See, Wen-Jay Lee, Tai-Yue Li, Nan-Yow Chen, Tian-Li Wu