The paper presents neural‑network (NN) transistor models that predict drain current and charges for a 3 nm nanosheet, and applies them to standard cell library characterization. The NN models achieve sub‑0.11 % error in delay and 0.76 % in total power across a wide range of circuits, while reducing characterization time by up to eight times compared to the industry‑standard Verilog‑A BSIM‑CMG model. The study also explores how NN size affects simulation precision and provides guidance for accurate circuit simulation.
arXiv:2609.13200v1 Announce Type: cross Abstract: Compact transistor models are the mathematical backbone of circuit simulation. However, at advanced nodes such as 3nm, transport physics becomes too...
arXiv:2606. 24046v1 Announce Type: cross Abstract: This work presents a machine learning framework that leverages an autoencoder (AE) for the efficient modeling of FinFET.
arXiv:2507.05134v2 Announce Type: replace Abstract: We present a deep learning approach to extract physical parameters (e.g., mobility, Schottky contact barrier height, defect profiles) of two-dimens...
The article presents the first demonstration of an agentic TCAD calibration workflow for a fabricated bottom‑gate In–W–O transistor. Starting from measured transfer curves, the workflow uses measurement–TCAD residuals and local sensitivity tests to guide parameter corrections or additional physical models, accepting only updates that improve device metrics. For a 2%‑W reference device, five agent‑suggested updates reduced the multi‑metric device objective by 14.3× and achieved low errors in threshold voltage and on‑current across varying bias and geometry, showing model transferability and process sensitivity.
The paper introduces a physics‑informed graph attention network that directly operates on the tetrahedral mesh used in TCAD simulations of FinFET devices. By predicting electrostatic potential and quasi‑Fermi levels at every mesh node and training with both data loss and finite‑volume current‑continuity residuals, the surrogate retains the underlying carrier‑transport physics while achieving size generalization. Benchmarks against Sentaurus Device show sub‑volt RMSE for the drift‑diffusion fields and a per‑design throughput that is orders of magnitude faster, enabling rapid Pareto‑front exploration of large multi‑fin arrays that would otherwise be prohibitively slow to simulate.
arXiv:2603. 13042v2 Announce Type: replace Abstract: Digital Compute-in-Memory (DCiM) accelerates neural networks by reducing data movement.
arXiv:2607. 05187v1 Announce Type: new Abstract: As CMOS technology scales into the deep nanometer regime, digital circuit reliability is increasingly threatened by the combined stochastic effects of Bias Temperature Instability (BTI) and Process Variation (PV).
The paper proposes a hardware-software co-design to mitigate voltage scaling errors in deep neural networks. It introduces Accumulation-Aware Training that constrains weight distributions, combines mixed-precision quantization with pruning, and applies selective MSB-masking, clock-gating, and layer-wise dynamic frequency scaling. Experiments on a 2nm node show 39% energy savings and 23% energy-delay product improvement at low voltage, with less than 1% accuracy loss.
arXiv:2607. 23225v1 Announce Type: new Abstract: As chip manufacturing processes advance to deep submicron nodes, parasitic interconnect effects increasingly dominate the performance of analog and mixed-signal (AMS) circuits and often lead to costly layout iterations.
The paper presents a Physics Informed Neural Network (PINN) approach to solve the drift‑diffusion equations that govern semiconductor devices. By applying advanced training techniques, the authors achieve errors comparable to commercial TCAD software while handling extreme gradients and discontinuities in a PN‑junction. The method also enables inverse design, retrieving doping profiles from desired electric field or potential distributions under non‑equilibrium bias conditions.
As CMOS technology scales into the deep nanometer regime, digital circuit reliability is increasingly threatened by the combined stochastic effects of Bias Temperature Instability (BTI) and Process Variation (PV). Traditional reliability analysis methods, which rely on computationally intensive simulations or extensive lookup tables, fail to scale efficiently for large designs, creating a critical bottleneck in design space exploration.
arXiv:2607. 08427v1 Announce Type: cross Abstract: Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications.