arXiv Machine Learning July 28, 2026 By Jiajun Zou, Jiawei Liu, Ao Liu, Junnong Tian, Yibin Zhang, Chengjie Liu, Yuxi Wang, Shan Shen, Wenhua Gu, Jun Yang, Wenjian Yu

ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuits

Read the original on arXiv Machine Learning →

arXiv:2607. 23225v1 Announce Type: new Abstract: As chip manufacturing processes advance to deep submicron nodes, parasitic interconnect effects increasingly dominate the performance of analog and mixed-signal (AMS) circuits and often lead to costly layout iterations.

Machine-generated by The Flow from the publisher's headline and feed description — not written or checked by a human. The full article lives at arXiv Machine Learning.

benchmarks

arXiv Machine Learning

Jun 9

CTS-Bench: Benchmarking Graph Coarsening Trade-offs for GNNs in Clock Tree Synthesis

arXiv:2602. 19330v2 Announce Type: replace Abstract: Graph Neural Networks (GNNs) are increasingly explored for physical design analysis in Electronic Design Automation, particularly for modeling Clock Tree Synthesis behavior such as clock skew and buffering complexity.

By Barsat Khadka, Kawsher Roxy, Md Rubel Ahmed

benchmarks

arXiv AI

Jun 8

VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification

arXiv:2603. 11075v3 Announce Type: replace-cross Abstract: As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows.

By Runbang Hu, Bo Fang, Bingzhe Li, Yuede Ji

benchmarks

arXiv Machine Learning

4d ago

cktFormer: Transformer-Based Approach for Automated Analog Circuit Design

arXiv:2609.36752v1 Announce Type: new Abstract: Circuit design is a complex and iterative process that requires expertise in electronic engineering. It involves selecting components while meeting per...

By Pasindu Dodampegama, Praveen Wijesinghe, Naveen Basnayake, Keshawa Jayasundara, Tharindu Bandaragoda

llms benchmarks

arXiv Machine Learning

Aug 31

Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits

arXiv:2608.28188v1 Announce Type: new Abstract: Circuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical...

By Jingyi Zhou, Zhengyuan Shi, Jiaying Zhu, Ziyang Zheng, Qiang Xu

benchmarks

arXiv Machine Learning

Jul 16

RF-Informed Graph Neural Networks for Accurate and Data-Efficient Circuit Performance Prediction

arXiv:2508. 16403v3 Announce Type: replace Abstract: Accurately predicting the performance of active radio frequency (RF) circuits is essential for modern wireless systems but remains challenging due to highly nonlinear behavior and the high computational cost of traditional simulation tools.

By Anahita Asadi, Leonid Popryho, Inna Partin-Vaisband

multimodal benchmarks

arXiv Machine Learning

Jul 8

Leveraging Neural Graph Compilers in Machine Learning Research for Edge-Cloud Systems

arXiv:2504. 20198v2 Announce Type: replace-cross Abstract: This work presents a comprehensive evaluation of neural network graph compilers across heterogeneous hardware platforms, addressing the critical gap between theoretical optimization techniques and practical deployment scenarios.

By Alireza Furutanpey, Carmen Walser, Philipp Raith, Pantelis A. Frangoudis, Schahram Dustdar

efficiency

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