The paper introduces REQAP, a reliability‑aware quantized weight packing technique for systolic‑array DNN accelerators. It uses a sensitivity‑driven mixed‑precision quantization to assign layer‑wise bit‑widths, a deterministic register‑level packing strategy for SIMD‑within‑a‑register execution, and selective bit‑level protection that replicates critical MSBs into unused register space. Experiments on AlexNet, VGG‑11, and ResNet‑18 show up to 62% memory reduction, 56% fewer MAC operations, and improved accuracy resilience under fault injection compared to baseline and fully protected models.
By Mahdi Taheri, Samira Nazari, Mubassher Ansari, Ali Azarpeyvand, Mohsen Afsharchi, Maksim Jenihhin, Christian Herglotz
arXiv:2608. 02700v1 Announce Type: cross Abstract: Analog compute-in-memory (CIM) enables energy-efficient neural network inference, but device variation and read noise can severely degrade low-bit quantized models.
By Yizhe Chen, Wenshuai Yao, Saiya Wang, Yuannuo Feng, Wenbo Qi, Kechao Tang, Ngai Wong, Wenyong Zhou, Wang Kang
arXiv:2603. 13042v2 Announce Type: replace Abstract: Digital Compute-in-Memory (DCiM) accelerates neural networks by reducing data movement.
By Yiqi Zhou, Yue Yuan, Yikai Wang, Bohao Liu, Qinxin Mei, Zhuohua Liu, Shan Shen, Wei Xing, Daying Sun, Li Li, Guozhu Liu
HBQ: Hierarchical Scaling Block Quantization with Hardware‑Efficiency‑Aware Design for Accurate LLM Inference proposes a new block‑quantization scheme that uses large blocks and low‑overhead significand scaling to balance hardware efficiency and accuracy. The authors demonstrate that larger blocks improve efficiency by amortizing dequantization and accumulation costs, while their SIG scaling compensates for the resulting accuracy loss. Experiments on a 28 nm ASIC accelerator show that HBQ achieves up to 4.6× higher area/energy efficiency than state‑of‑the‑art weight‑only quantization, with 1.5–3.0× speedup and 1.6–3.3× system energy reduction over existing BQ methods.
By Chun-Ting Chen, Dongmin Han, Hangyeol Mun, Jake Hyun, Arnab Raha, Amit Agarwal, Mark Anders, Mohamed Abdelfattah, Jae-sun Seo
arXiv:2512.04705v3 Announce Type: replace-cross
Abstract: The deployment of Early-Exiting Neural Networks (EENNs) on edge accelerators requires optimizing not only the network architecture but also i...
By Alaa Zniber, Arne Symons, Ouassim Karrakchou, Marian Verhelst, Mounir Ghogho
FAME is an FPGA-based platform that evaluates approximate multipliers directly in hardware, eliminating slow CPU/GPU LUT emulation and reducing evaluation time for DNN inference. It also introduces a pattern-guided retraining method that uses multiplier-specific patterns to recover accuracy losses. Experiments on ResNet‑18 and MobileNetV2 over ImageNet show up to 3.47× faster multiplier evaluation and a 65.5% accuracy improvement over prior retraining approaches.
By Rappy Saha, Nima Amirafshar, Jude Haris, Nima Taherinejad, Jos\'e Cano
The paper investigates how temperature affects analog deep neural network (DNN) inference, focusing on both stochastic and systematic non‑idealities in analog hardware. Experiments show that temperature‑induced performance loss is mainly driven by systematic errors rather than random noise. The study evaluates various mitigation techniques, finding that noise‑aware training and temperature‑aware calibration—especially hardware‑in‑the‑loop training—best preserve inference accuracy across different thermal conditions.
By Niklas Summ, Xiao Wang, Hendrik Borras, Bernhard Klein, Holger Fr\"oning
arXiv:2606. 17249v1 Announce Type: cross Abstract: The dominant trajectory of modern machine learning has been to scale up: larger models, larger accelerators, larger memory budgets.
By Emre Can Kizilates
arXiv:2609.36584v1 Announce Type: new
Abstract: Analog in-memory computing (AIMC) offers an alternative for model training by executing matrix operations directly where weights are stored. However, s...
By Zhaoxian Wu, Tayfun Gokmen, Omobayode Fagbohungbe, T. Patrick Xiao, Tianyi Chen
The paper introduces RAMP, a method for robust adaptive mixed‑precision quantization of vision models on edge CPUs. It evaluates 13 sensitivity metrics across four neural networks, finding that Jensen‑Shannon Divergence consistently identifies layers that can be safely quantized. Using K‑Means clustering on these metrics, RAMP achieves near‑lossless accuracy with an average 1.81× speed‑up, while cautioning against excluding low‑speed‑up layers that can fragment the computational graph.
By David Poblaci\'on-Criado, Dario Garcia-Gasulla, Eduardo Quinones
The paper introduces a spike‑aware, gradient‑based mixed‑precision quantization framework for Spiking Neural Networks (SNNs), which assigns bit‑widths adaptively using first‑order gradient information. This approach avoids the memory and computational overhead of Hessian‑based methods like HAWQ‑V2 and is evaluated on VGG, ResNet, and Vision Transformer architectures across CIFAR‑10/100, ImageNet, and DVS‑CIFAR‑10 datasets. On ResNet‑34 with ImageNet, the method attains 73.30% accuracy at 4.78× compression, matching HAWQ‑V2 while reducing memory usage by 2.31× and bit‑allocation runtime by 100×, and it demonstrates energy‑efficient deployment without performance loss.
By Rajshekhar Rakshit, Devgokul B. V, Rakshitha Kalkura, Gopalakrishnan Srinivasan
arXiv:2602. 23334v2 Announce Type: replace-cross Abstract: Neural network accelerators have been widely applied to edge devices for complex tasks like object tracking, image recognition, etc.
By Yuhao Liu, Salim Ullah, Akash Kumar