The paper introduces a Bounded Dual-Loop Automated Schematic Synthesis Framework that converts natural language specifications into verified KiCad schematics and manufacturing deliverables for power electronics converters. It integrates six stages across three functional columns: requirement parsing and topology synthesis, evidence‑driven component selection with distributor APIs and datasheets, and modular control hardware integration with multi‑format deliverable generation. End‑to‑end case studies on Buck and Dual‑Active Bridge converters show significant improvements in component verification coverage, nominal value consistency, and SPICE simulation pass rates compared to a vanilla LLM baseline.
By Bowen Su, Huan Chen, Jiahua Ying, Ran Ou, Weilong Chen, Li Xue, Kai Sun
arXiv:2606. 01188v1 Announce Type: cross Abstract: Translating natural-language hardware requirements into correct printed circuit board (PCB) schematics remains difficult in embedded, IoT, and wearable development.
By Tobias King, Steven Kehrberg, Michael Beigl, Tobias R\"oddiger
arXiv:2608. 13472v1 Announce Type: cross Abstract: Analog circuit design is a time-consuming, iterative process in a nonlinear and high-dimensional design space that relies heavily on expert intuition.
By Mohammed Ayman Habib, Rylan Hart, Morteza Fayazi
arXiv:2607. 01609v1 Announce Type: new Abstract: Recent advances in Artificial Intelligence (AI) have revolutionized Electronic Design Automation (EDA), particularly through Large Language Models (LLMs) for circuit design tasks.
By Saoud Aldowaish, Yashwanth Karumanchi, Kai-Chen Chiang, Mohammed Ayman Habib, Finn Murphy, Rishen Cao, Morteza Fayazi
Recent advances in Artificial Intelligence (AI) have revolutionized Electronic Design Automation (EDA), particularly through Large Language Models (LLMs) for circuit design tasks. However, their application to analog and mixed-signal domains remains limited by the lack of machine-readable representations of existing circuit design knowledge.
arXiv:2607. 03835v1 Announce Type: cross Abstract: Converting a SPICE netlist into a human-readable schematic is a longstanding problem in electronic design automation: simulators and machine-learning pipelines readily produce netlists, but designers reason about circuits through diagrams.
By Senol Gulgonul
arXiv:2607. 14165v1 Announce Type: cross Abstract: While Large Language Models (LLMs) have demonstrated significant capability in software code generation, their application to analog Electronic Design Automation (EDA) is bottlenecked.
By Dimple Vijay Kochar, Hae-Seung Lee, Anantha P. Chandrakasan
The paper introduces VHDLBench, a benchmark and fine‑tuning framework for large language models (LLMs) applied to VHDL-based chip design. It presents a dataset of over 18,500 syntax‑verified VHDL examples, fine‑tunes five 7B‑parameter LLMs with QLoRA, and evaluates them through a three‑level pipeline—syntax/synthesis validation, functional simulation, and FPGA prototyping on Zynq SoCs. Results show up to 92% syntax correctness and 73% functional accuracy, with DeepSeek‑Coder achieving the best performance and successful deployment on real hardware.
By Patrik Drazic, Benaoumeur Senouci, Boualem Benatallah
Analog-DB is an open‑source, versioned database that stores analog integrated circuit designs in a process‑neutral topology, reusable testbenches, and machine‑readable datasheets using a domain‑specific language. The database’s parameterization scheme and schema‑governed contracts enable AI design agents to discover, compose, and retarget circuits across multiple process kits. In a case study, a coding agent used the released artifacts to size op‑amp cores for a chopper instrumentation amplifier, uncovering defects that a sizing‑only baseline missed.
By Danial Noori Zadeh, Mohamed B. Elamien
arXiv:2504. 03711v2 Announce Type: replace-cross Abstract: Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications.
By Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Yuchao Wu, Yuzhe Ma, Zhiyao Xie
Sharing analog integrated circuit designs remains difficult: foundry non-disclosure agreements restrict the process details a design depends on, and the testbenches behind published results are rarely...
arXiv:2610.09549v1 Announce Type: new
Abstract: And-Inverter Graphs (AIGs) are fundamental representations for logic synthesis and verification in Electronic Design Automation (EDA). As structured re...
By Qifan Zhang, Ruijie Li, Fangzhou Zhang, Qian Ma, Hui Li, Furui Zhan, Yongpeng Wang, Liying Hao, Shikai Guo