arXiv AI By Bowen Su, Huan Chen, Jiahua Ying, Ran Ou, Weilong Chen, Li Xue, Kai Sun

From Natural Language to Real Schematics: An Automated Workflow for Power Electronics Schematic Synthesis

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The paper introduces a Bounded Dual-Loop Automated Schematic Synthesis Framework that converts natural language specifications into verified KiCad schematics and manufacturing deliverables for power electronics converters. It integrates six stages across three functional columns: requirement parsing and topology synthesis, evidence‑driven component selection with distributor APIs and datasheets, and modular control hardware integration with multi‑format deliverable generation. End‑to‑end case studies on Buck and Dual‑Active Bridge converters show significant improvements in component verification coverage, nominal value consistency, and SPICE simulation pass rates compared to a vanilla LLM baseline.

Machine-generated by The Flow from the publisher's headline and feed description — not written or checked by a human. The full article lives at arXiv AI.

arXiv Machine Learning
Jul 3

SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence

arXiv:2607. 01609v1 Announce Type: new Abstract: Recent advances in Artificial Intelligence (AI) have revolutionized Electronic Design Automation (EDA), particularly through Large Language Models (LLMs) for circuit design tasks.

By Saoud Aldowaish, Yashwanth Karumanchi, Kai-Chen Chiang, Mohammed Ayman Habib, Finn Murphy, Rishen Cao, Morteza Fayazi
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SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence

Recent advances in Artificial Intelligence (AI) have revolutionized Electronic Design Automation (EDA), particularly through Large Language Models (LLMs) for circuit design tasks. However, their application to analog and mixed-signal domains remains limited by the lack of machine-readable representations of existing circuit design knowledge.

arXiv AI
Oct 23

VHDLBench: Benchmarking and Fine-Tuning Large Language Models for VHDL-Based Chip Design

The paper introduces VHDLBench, a benchmark and fine‑tuning framework for large language models (LLMs) applied to VHDL-based chip design. It presents a dataset of over 18,500 syntax‑verified VHDL examples, fine‑tunes five 7B‑parameter LLMs with QLoRA, and evaluates them through a three‑level pipeline—syntax/synthesis validation, functional simulation, and FPGA prototyping on Zynq SoCs. Results show up to 92% syntax correctness and 73% functional accuracy, with DeepSeek‑Coder achieving the best performance and successful deployment on real hardware.

By Patrik Drazic, Benaoumeur Senouci, Boualem Benatallah