arXiv Machine Learning
CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphs
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A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
arXiv:2504. 03711v2 Announce Type: replace-cross Abstract: Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications.
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TRACE: Learning to Compute on Circuit Graphs
arXiv:2509. 21886v3 Announce Type: replace Abstract: Learning to compute, the ability to model the functional behavior of a circuit graph, is a fundamental challenge for graph representation learning.
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Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits
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Hugging Face Trending Papers
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LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks
LevelSyn introduces a physical-aware logic synthesis framework that uses a level-asynchronous Graph Neural Network to predict accurate gate coordinates by learning the structural and directional semantics of And-Inverter Graphs. It incorporates a level-aligned subgraph partitioning strategy to handle large designs and integrates these spatial insights into a new synthesis engine within the Berkeley ABC framework. Experiments on the EPFL benchmark suite show significant improvements, with an average power reduction of 6.89%, a timing delay improvement of 27.48%, and a 99.59% reduction in design rule check violations.
arXiv AI
Sep 4
LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks
LevelSyn is a physical-aware logic synthesis framework that uses a level-asynchronous Graph Neural Network to predict high-fidelity gate coordinates by learning the structural and directional semantics of And-Inverter Graphs. It incorporates a level-aligned subgraph partitioning strategy to manage industrial-scale designs and integrates these spatial insights into a new synthesis engine within the Berkeley ABC framework. Experiments on the EPFL benchmark suite show LevelSyn outperforms state-of-the-art methods, achieving an average power reduction of 6.89%, a timing delay improvement of 27.48%, and a 99.59% reduction in design rule check violations.
arXiv Machine Learning
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cktFormer: Transformer-Based Approach for Automated Analog Circuit Design
arXiv:2609.36752v1 Announce Type: new Abstract: Circuit design is a complex and iterative process that requires expertise in electronic engineering. It involves selecting components while meeting per...