arXiv AI July 17, 2026 By Dimple Vijay Kochar, Hae-Seung Lee, Anantha P. Chandrakasan

Towards Reliable AI-Assisted Analog Design: Template-Constrained LLM Agents for SAR ADC Generation

arXiv:2607. 14165v1 Announce Type: cross Abstract: While Large Language Models (LLMs) have demonstrated significant capability in software code generation, their application to analog Electronic Design Automation (EDA) is bottlenecked.

Machine-generated by The Flow from the publisher's headline and feed description — not written or checked by a human. The full article lives at arXiv AI.

arXiv AI

Aug 14

AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models

arXiv:2608. 13472v1 Announce Type: cross Abstract: Analog circuit design is a time-consuming, iterative process in a nonlinear and high-dimensional design space that relies heavily on expert intuition.

By Mohammed Ayman Habib, Rylan Hart, Morteza Fayazi

llms rag agents benchmarks safety

Hugging Face Trending Papers

Sep 22

AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing

Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled technologies. Although rec...

llms agents benchmarks safety

arXiv AI

Aug 17

Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement

arXiv:2608. 13767v1 Announce Type: new Abstract: Analog IC layout design remains a labor-intensive iterative process dominated by simulation-driven refinement.

By Bingyang Liu, Ziming Wei, Xiaohan Gao, David Z. Pan

llms agents

arXiv Machine Learning

Jun 5

CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs

arXiv:2606. 05680v1 Announce Type: cross Abstract: Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design.

By Mohammad Akyash, Nowfel Mashnoor, Kimia Azar, Hadi Kamali

llms rag agents fine-tuning safety

arXiv Machine Learning

Jul 16

EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models

arXiv:2607. 13416v1 Announce Type: new Abstract: Automating analog circuit topology design is essential to reduce the extensive manual effort required to meet increasingly diverse and customized application demands.

By Guanglei Zhou, Chen-Chia Chang, Yikang Shen, Jonathan Ku, Isaac Jacobson, Jingyu Pan, Yiran Chen, Xin Zhang

llms fine-tuning benchmarks

arXiv Machine Learning

Jul 13

LLM for EDA in Front-End Design: Challenges and Opportunities

arXiv:2607. 09616v1 Announce Type: cross Abstract: As chip complexity increases and time-to-market pressures grow, front-end design has become a critical bottleneck in chip development.

By Kangwei Xu, Bing Li, Ulf Schlichtmann

llms agents

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Related stories

AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models

AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing

Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement

CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs

EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models

LLM for EDA in Front-End Design: Challenges and Opportunities