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arXiv AI By Patrik Drazic, Benaoumeur Senouci, Boualem Benatallah

VHDLBench: Benchmarking and Fine-Tuning Large Language Models for VHDL-Based Chip Design

Read the original on arXiv AI →

The paper introduces VHDLBench, a benchmark and fine‑tuning framework for large language models (LLMs) applied to VHDL-based chip design. It presents a dataset of over 18,500 syntax‑verified VHDL examples, fine‑tunes five 7B‑parameter LLMs with QLoRA, and evaluates them through a three‑level pipeline—syntax/synthesis validation, functional simulation, and FPGA prototyping on Zynq SoCs. Results show up to 92% syntax correctness and 73% functional accuracy, with DeepSeek‑Coder achieving the best performance and successful deployment on real hardware.

Machine-generated by The Flow from the publisher's headline and feed description — not written or checked by a human. The full article lives at arXiv AI.

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