arXiv AI

Towards Reliable AI-Assisted Analog Design: Template-Constrained LLM Agents for SAR ADC Generation

arXiv:2607. 14165v1 Announce Type: cross Abstract: While Large Language Models (LLMs) have demonstrated significant capability in software code generation, their application to analog Electronic Design Automation (EDA) is bottlenecked.

arXiv AI

Aug 14

AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models

arXiv:2608. 13472v1 Announce Type: cross Abstract: Analog circuit design is a time-consuming, iterative process in a nonlinear and high-dimensional design space that relies heavily on expert intuition.

By Mohammed Ayman Habib, Rylan Hart, Morteza Fayazi

llms rag agents benchmarks safety

Hugging Face Trending Papers

Sep 22

AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing

Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled technologies. Although rec...

llms agents benchmarks safety

arXiv AI

Aug 17

Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement

arXiv:2608. 13767v1 Announce Type: new Abstract: Analog IC layout design remains a labor-intensive iterative process dominated by simulation-driven refinement.

By Bingyang Liu, Ziming Wei, Xiaohan Gao, David Z. Pan

llms agents

arXiv Machine Learning

Jun 5

CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs

arXiv:2606. 05680v1 Announce Type: cross Abstract: Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design.

By Mohammad Akyash, Nowfel Mashnoor, Kimia Azar, Hadi Kamali

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arXiv Machine Learning

Jul 16

EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models

arXiv:2607. 13416v1 Announce Type: new Abstract: Automating analog circuit topology design is essential to reduce the extensive manual effort required to meet increasingly diverse and customized application demands.

By Guanglei Zhou, Chen-Chia Chang, Yikang Shen, Jonathan Ku, Isaac Jacobson, Jingyu Pan, Yiran Chen, Xin Zhang

llms fine-tuning benchmarks

arXiv Machine Learning

Jul 13

LLM for EDA in Front-End Design: Challenges and Opportunities

arXiv:2607. 09616v1 Announce Type: cross Abstract: As chip complexity increases and time-to-market pressures grow, front-end design has become a critical bottleneck in chip development.

By Kangwei Xu, Bing Li, Ulf Schlichtmann

llms agents

arXiv AI

Aug 20

Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead

The article reviews the growing use of Large Language Models (LLMs) for generating Verilog code, a key hardware description language in electronic design automation. It surveys 102 papers, covering conferences, journals, and preprints, and addresses four research questions about LLM selection, datasets, techniques, and alignment strategies. The review identifies current limitations and proposes a roadmap for future research in LLM-assisted hardware design.

By Guang Yang, Wei Zheng, Xiang Chen, Dong Liang, Peng Hu, Yukui Yang, Shaohang Peng, Zhenghan Li, Jiahui Feng, Xiao Wei, Kexin Sun, Deyuan Ma, Haotian Cheng, Yiheng Shen, Xing Hu, Terry Yue Zhuo, David Lo

llms safety

arXiv AI

Jun 19

Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement

arXiv:2606. 19387v1 Announce Type: cross Abstract: Large language models (LLMs) have achieved remarkable success in software development.

By You Li, Samuel Mandell, David Z. Pan

llms agents safety

arXiv AI

Jun 4

StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis

arXiv:2606. 04246v1 Announce Type: new Abstract: Automatic generation of RTL code for digital hardware designs remains challenging due to long-horizon reasoning, multi-step dependencies, and strict correctness constraints in Verilog and VHDL.

By Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi, Ehsan Degan, Vandana Mukherjee

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arXiv Machine Learning

Jul 28

Can an Actor-Critic Optimization Framework Improve Analog Design?

arXiv:2603. 24714v2 Announce Type: replace Abstract: Analog design often slows down because even small changes to device sizes or biases require expensive simulation cycles, and high-quality solutions typically occupy only a narrow part of a very large search space.

By Sounak Dutta, Fin Amin, Sushil Panda, Jonathan Rabe, Yuejiang Wen, Paul Franzon

arXiv Machine Learning

Jul 7

SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows

arXiv:2607. 03701v1 Announce Type: cross Abstract: Large language models (LLMs) can propose circuit-optimization decisions, but industrial analog flows cannot expose foundry PDK content, proprietary schematics, absolute simulation paths, or license-bound tool state to a cloud endpoint.

By Xunqi Li, Chris H. Kim

llms safety

arXiv AI

Aug 6

ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration

arXiv:2608. 04999v1 Announce Type: cross Abstract: Analog circuit design automation using reinforcement learning (RL) has emerged as a promising approach for reducing manual effort.

By Osei Brempong, Mohammed Ayman Habib, Vivan Poddar, Morteza Fayazi

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