arXiv:2606. 01188v1 Announce Type: cross Abstract: Translating natural-language hardware requirements into correct printed circuit board (PCB) schematics remains difficult in embedded, IoT, and wearable development.
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QiMeng-ChipV-RTL is a multi‑agent framework that tackles the challenges of generating Register‑Transfer Level (RTL) code for industrial IP‑level hardware design. By partitioning long design documents into short, localized tasks and using hierarchical planning, localized code generation, interface‑consistent merging, and AST‑guided debugging, it scales to complex specifications. Experiments on the RealBench benchmark show ChipV-RTL achieves a 45.0% pass rate, outperforming state‑of‑the‑art LLMs and agents which reach only 21.6%.
Recent advances in large language models and programmatic CAD have significantly improved Text-to-CAD generation for individual parts. However, production-ready mechanical assembly generation remains largely unsolved.
arXiv:2607. 05123v1 Announce Type: new Abstract: Recent advances in large language models and programmatic CAD have significantly improved Text-to-CAD generation for individual parts.
arXiv:2606. 17074v1 Announce Type: cross Abstract: Generative artificial intelligence (GenAI) is increasingly used for applications in the hardware and software domains.
PCBnet is a new large‑scale dataset of printed circuit board (PCB) schematics that includes over 300 real‑world designs, more than 50,000 component instances, 150,000 wires, 100,000 text regions, and 400,000 characters, each paired with a SPICE netlist. The authors also introduce an automated pipeline that converts schematic images into netlists, achieving 94.54% component detection mAP, 98.57% text recognition accuracy, and 84.47% end‑to‑end connectivity accuracy. This resource aims to serve as a benchmark and data foundation for future AI‑driven PCB design automation.
arXiv:2607. 09616v1 Announce Type: cross Abstract: As chip complexity increases and time-to-market pressures grow, front-end design has become a critical bottleneck in chip development.