TARGet is an open‑source, topology‑aware machine‑learning framework for modeling RF circuits. It uses S‑parameter representations of sub‑circuits and a fusion architecture that combines Graph Neural Networks with sub‑circuit connectivity‑aware networks, enabling learning across multiple topologies. Experiments show TARGet achieves sub‑1% prediction error, reduces training data needs by up to 35.5×, and improves accuracy by 9.7× over state‑of‑the‑art models, with zero‑shot transfer to unseen sub‑circuit topologies.
arXiv:2508. 16403v3 Announce Type: replace Abstract: Accurately predicting the performance of active radio frequency (RF) circuits is essential for modern wireless systems but remains challenging due to highly nonlinear behavior and the high computational cost of traditional simulation tools.
The paper presents an end-to-end neural framework that predicts electromagnetic (EM) response and design performance for free-form RFIC passive matching networks across varying frequencies and circuit contexts. It combines a frequency-conditioned neural simulator with a circuit-conditioned neural solver, outputting both explicit EM response and a complementary response to capture orthogonal information. The 21‑million‑parameter model, trained on a large dataset of expert‑designed and random passive layouts, achieves $R^2>0.98$ for most targets and is orders of magnitude faster than traditional EM simulation.
arXiv:2609.36752v1 Announce Type: new Abstract: Circuit design is a complex and iterative process that requires expertise in electronic engineering. It involves selecting components while meeting per...
arXiv:2509. 21886v3 Announce Type: replace Abstract: Learning to compute, the ability to model the functional behavior of a circuit graph, is a fundamental challenge for graph representation learning.
arXiv:2610.09549v1 Announce Type: new Abstract: And-Inverter Graphs (AIGs) are fundamental representations for logic synthesis and verification in Electronic Design Automation (EDA). As structured re...
ReDIL-GNN is a framework for resynthesis domain‑incremental learning in circuit graph neural networks. It adapts a fixed prediction or representation head as new synthesis styles appear and evaluates retention across all previously seen domains. The method introduces the Resynthesis Adaptability Index (RAI), a pre‑adaptation score that combines adaptation need, source‑equivalence recoverability, structural coverage, and update compatibility to decide whether to adapt, reuse, or defer updates.
arXiv:2504. 03711v2 Announce Type: replace-cross Abstract: Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications.
arXiv:2608. 12687v1 Announce Type: new Abstract: Bayesian optimization (BO) is a sample-efficient framework for analog circuit topology search, where evaluating each candidate topology can require costly simulation.
arXiv:2603. 09161v2 Announce Type: replace-cross Abstract: Learning effective netlist representations is fundamentally constrained by the scarcity of labeled datasets, as real designs are protected by Intellectual Property (IP) and costly to annotate.
arXiv:2610.20209v1 Announce Type: new Abstract: Routability prediction enables rapid evaluation of placement quality without routing, providing effective feedback for routability-driven placement opt...
arXiv:2607. 23225v1 Announce Type: new Abstract: As chip manufacturing processes advance to deep submicron nodes, parasitic interconnect effects increasingly dominate the performance of analog and mixed-signal (AMS) circuits and often lead to costly layout iterations.
arXiv:2602. 01553v3 Announce Type: replace-cross Abstract: Link prediction is a core challenge in graph machine learning, demanding models that capture rich and complex topological dependencies.