arXiv:2603. 11075v3 Announce Type: replace-cross Abstract: As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows.
arXiv:2509. 21886v3 Announce Type: replace Abstract: Learning to compute, the ability to model the functional behavior of a circuit graph, is a fundamental challenge for graph representation learning.
The paper presents a unified benchmark of graph neural network (GNN) architectures for predicting AC power flow (ACPF) on IEEE 14‑bus and 118‑bus systems. It isolates the effects of message‑passing mechanisms and inductive biases by using identical preprocessing, training procedures, and comparable parameter budgets. The study finds that anisotropic message‑passing, explicit edge features for line impedances, and global context aggregation yield the best trade‑off between predictive accuracy and physical consistency, while two or three message‑passing layers are generally optimal under a fixed parameter budget.
arXiv:2610.09549v1 Announce Type: new Abstract: And-Inverter Graphs (AIGs) are fundamental representations for logic synthesis and verification in Electronic Design Automation (EDA). As structured re...
LevelSyn introduces a physical-aware logic synthesis framework that uses a level-asynchronous Graph Neural Network to predict accurate gate coordinates by learning the structural and directional semantics of And-Inverter Graphs. It incorporates a level-aligned subgraph partitioning strategy to handle large designs and integrates these spatial insights into a new synthesis engine within the Berkeley ABC framework. Experiments on the EPFL benchmark suite show significant improvements, with an average power reduction of 6.89%, a timing delay improvement of 27.48%, and a 99.59% reduction in design rule check violations.
arXiv:2605.23194v2 Announce Type: replace-cross Abstract: Fast and reliable optimal power flow (OPF) approximation is important for power system operation, yet heterogeneous OPF graph models are ofte...
TARGet is an open‑source, topology‑aware machine‑learning framework for modeling RF circuits. It uses S‑parameter representations of sub‑circuits and a fusion architecture that combines Graph Neural Networks with sub‑circuit connectivity‑aware networks, enabling learning across multiple topologies. Experiments show TARGet achieves sub‑1% prediction error, reduces training data needs by up to 35.5×, and improves accuracy by 9.7× over state‑of‑the‑art models, with zero‑shot transfer to unseen sub‑circuit topologies.
The paper presents a hierarchical reinforcement learning framework for jointly optimizing routing and switch placement in chip design. It builds solutions from a minimal routing graph using three operations—switch expansion, switch placement, and route refinement—that maintain routing validity by construction. Neural‑guided Gumbel Monte Carlo Tree Search and pretraining across floorplans are shown to improve solution quality over non‑learning methods.
arXiv:2508. 16403v3 Announce Type: replace Abstract: Accurately predicting the performance of active radio frequency (RF) circuits is essential for modern wireless systems but remains challenging due to highly nonlinear behavior and the high computational cost of traditional simulation tools.
LevelSyn is a physical-aware logic synthesis framework that uses a level-asynchronous Graph Neural Network to predict high-fidelity gate coordinates by learning the structural and directional semantics of And-Inverter Graphs. It incorporates a level-aligned subgraph partitioning strategy to manage industrial-scale designs and integrates these spatial insights into a new synthesis engine within the Berkeley ABC framework. Experiments on the EPFL benchmark suite show LevelSyn outperforms state-of-the-art methods, achieving an average power reduction of 6.89%, a timing delay improvement of 27.48%, and a 99.59% reduction in design rule check violations.
arXiv:2602. 01553v3 Announce Type: replace-cross Abstract: Link prediction is a core challenge in graph machine learning, demanding models that capture rich and complex topological dependencies.
arXiv:2608. 01160v1 Announce Type: new Abstract: Topological neural networks (TNNs) enable leveraging high-order structures on graphs (e.