arXiv AI August 3, 2026 By Siyang Cai, Cangyuan Li, Haoyu Gao, Kun Wang, Yinhe Han, Ying Wang

Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL

arXiv:2603. 09161v2 Announce Type: replace-cross Abstract: Learning effective netlist representations is fundamentally constrained by the scarcity of labeled datasets, as real designs are protected by Intellectual Property (IP) and costly to annotate.

Machine-generated by The Flow from the publisher's headline and feed description — not written or checked by a human. The full article lives at arXiv AI.

arXiv Machine Learning

Jul 3

A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

arXiv:2504. 03711v2 Announce Type: replace-cross Abstract: Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications.

By Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Yuchao Wu, Yuzhe Ma, Zhiyao Xie

llms fine-tuning

arXiv Machine Learning

Jun 5

CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs

arXiv:2606. 05680v1 Announce Type: cross Abstract: Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design.

By Mohammad Akyash, Nowfel Mashnoor, Kimia Azar, Hadi Kamali

llms rag agents fine-tuning safety

arXiv AI

Jun 17

TRACE: Learning to Compute on Circuit Graphs

arXiv:2509. 21886v3 Announce Type: replace Abstract: Learning to compute, the ability to model the functional behavior of a circuit graph, is a fundamental challenge for graph representation learning.

By Ziyang Zheng, Jiaying Zhu, Jingyi Zhou, Qiang Xu

llms benchmarks

arXiv Machine Learning

Sep 17

ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networks

ReDIL-GNN is a framework for resynthesis domain‑incremental learning in circuit graph neural networks. It adapts a fixed prediction or representation head as new synthesis styles appear and evaluates retention across all previously seen domains. The method introduces the Resynthesis Adaptability Index (RAI), a pre‑adaptation score that combines adaptation need, source‑equivalence recoverability, structural coverage, and update compatibility to decide whether to adapt, reuse, or defer updates.

By Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu

rag fine-tuning

arXiv AI

Aug 13

NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation

arXiv:2608. 12197v1 Announce Type: cross Abstract: Large Language Models (LLMs) are increasingly used in circuit design workflows, yet their reliability on simulator-facing SPICE netlist recognition and manipulation remains poorly understood and is rarely separated from high-level design reasoning.

By Jiarui Ma, Jianghan Wang, Yuheng Ma, Ziyi Zhuang, Xiaoguang Liu

llms robotics benchmarks

arXiv AI

Jun 16

Scalable Circuit Learning for Interpreting Large Language Models

arXiv:2606. 16939v1 Announce Type: cross Abstract: A prominent research direction in mechanistic interpretability is learning sparse circuits over LLM components to reveal how they jointly produce model behavior.

By Naiyu Yin, Dennis Wei, Tian Gao, Amit Dhurandhar, Karthikeyan Natesan Ramamurthy, Yue Yu

llms benchmarks safety

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Related stories

A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs

TRACE: Learning to Compute on Circuit Graphs

ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networks

NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation

Scalable Circuit Learning for Interpreting Large Language Models