arXiv Machine Learning
HGRP: Heterogeneous Graph Neural Network for Routability Prediction
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VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification
arXiv:2603. 11075v3 Announce Type: replace-cross Abstract: As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows.
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TRACE: Learning to Compute on Circuit Graphs
arXiv:2509. 21886v3 Announce Type: replace Abstract: Learning to compute, the ability to model the functional behavior of a circuit graph, is a fundamental challenge for graph representation learning.
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Benchmarking Graph Neural Networks for AC Power Flow: The Role of Inductive Biases and Physical Constraints
The paper presents a unified benchmark of graph neural network (GNN) architectures for predicting AC power flow (ACPF) on IEEE 14‑bus and 118‑bus systems. It isolates the effects of message‑passing mechanisms and inductive biases by using identical preprocessing, training procedures, and comparable parameter budgets. The study finds that anisotropic message‑passing, explicit edge features for line impedances, and global context aggregation yield the best trade‑off between predictive accuracy and physical consistency, while two or three message‑passing layers are generally optimal under a fixed parameter budget.
arXiv Machine Learning
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CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphs
arXiv:2610.09549v1 Announce Type: new Abstract: And-Inverter Graphs (AIGs) are fundamental representations for logic synthesis and verification in Electronic Design Automation (EDA). As structured re...
Hugging Face Trending Papers
Sep 3
LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks
LevelSyn introduces a physical-aware logic synthesis framework that uses a level-asynchronous Graph Neural Network to predict accurate gate coordinates by learning the structural and directional semantics of And-Inverter Graphs. It incorporates a level-aligned subgraph partitioning strategy to handle large designs and integrates these spatial insights into a new synthesis engine within the Berkeley ABC framework. Experiments on the EPFL benchmark suite show significant improvements, with an average power reduction of 6.89%, a timing delay improvement of 27.48%, and a 99.59% reduction in design rule check violations.
arXiv AI
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Scalable Heterogeneous Graph Foundation Models for Data-Driven Optimal Power Flow in Smart Grids
arXiv:2605.23194v2 Announce Type: replace-cross Abstract: Fast and reliable optimal power flow (OPF) approximation is important for power system operation, yet heterogeneous OPF graph models are ofte...