The paper presents a new conflict graph model for layout decomposition in DSA-MP, addressing overlooked edge-to-edge spacing constraints. It introduces a graph neural network–powered local refinement strategy that improves solution quality and convergence speed. Experiments show the method outperforms state‑of‑the‑art techniques across various scales, styles, nodes, and mask counts.
arXiv:2606. 00228v1 Announce Type: new Abstract: In semiconductor manufacturing, lithography projects circuit layouts onto silicon wafers through an optical mask.
LevelSyn introduces a physical-aware logic synthesis framework that uses a level-asynchronous Graph Neural Network to predict accurate gate coordinates by learning the structural and directional semantics of And-Inverter Graphs. It incorporates a level-aligned subgraph partitioning strategy to handle large designs and integrates these spatial insights into a new synthesis engine within the Berkeley ABC framework. Experiments on the EPFL benchmark suite show significant improvements, with an average power reduction of 6.89%, a timing delay improvement of 27.48%, and a 99.59% reduction in design rule check violations.
LevelSyn is a physical-aware logic synthesis framework that uses a level-asynchronous Graph Neural Network to predict high-fidelity gate coordinates by learning the structural and directional semantics of And-Inverter Graphs. It incorporates a level-aligned subgraph partitioning strategy to manage industrial-scale designs and integrates these spatial insights into a new synthesis engine within the Berkeley ABC framework. Experiments on the EPFL benchmark suite show LevelSyn outperforms state-of-the-art methods, achieving an average power reduction of 6.89%, a timing delay improvement of 27.48%, and a 99.59% reduction in design rule check violations.
arXiv:2602. 19330v2 Announce Type: replace Abstract: Graph Neural Networks (GNNs) are increasingly explored for physical design analysis in Electronic Design Automation, particularly for modeling Clock Tree Synthesis behavior such as clock skew and buffering complexity.
arXiv:2512. 16275v2 Announce Type: replace-cross Abstract: Automated floor plan generation lies at the intersection of combinatorial search, geometric constraint satisfaction, and functional design requirements -- a confluence that has historically resisted a unified computational treatment.
Large-scale topology optimization (TO) remains computationally demanding, especially for stress-constrained problems. To address this challenge, we propose the simultaneous neural topology optimizatio...
arXiv:2606. 04850v1 Announce Type: cross Abstract: Designing a neural network processor is an end-to-end co-design problem: network architecture and training budget determine the inference workload; hardware mapping decisions determine chip area, latency, and energy; and these characteristics govern fabrication yield and manufacturing cost.
TO-Agents is a multi‑agent AI framework that translates natural‑language design intent into iterative topology optimization. It converts a human problem description into solver inputs, runs the optimizer, renders 3D topologies, and employs a judge agent to critique and revise results using multiview vision‑language reasoning. Evaluated on a cantilever beam and a phone‑stand design, the system achieved preference‑aligned designs in 60% of trials, outperforming an ablated pipeline by up to six times and enabling end‑to‑end intent‑to‑prototype design with additive manufacturing.
The paper introduces the simultaneous neural topology optimization (SNTO) framework, which uses custom neural networks to jointly represent state, adjoint, and design variables in a single optimization loop. SNTO incorporates a multi-component loss function that balances design objectives, aggregated stress constraints, and potential energy, and employs a hardware‑aware training scheme that partitions the design domain across multiple GPUs to handle millions of degrees of freedom. Validation on 2D benchmarks shows super‑resolution designs with sharper boundaries and lower volume fractions, while large‑scale 3D tests demonstrate scalability to eight million collocation points on eight GPUs.
GraphCAD introduces a geometry-aware generative framework for Computer-Aided Design (CAD) that models CAD construction using an Edge-Adjacency Graph (EAG), a novel graph-based representation. The method employs a hybrid graph diffusion process to jointly capture discrete topological connectivity and continuous spatial geometry, and incorporates a geometry-aware denoising mechanism that maps node attributes to SE(3)-equivariant encoded point sets. Experiments on the newly created EAGBench dataset demonstrate that GraphCAD can generate complex CAD models with more than 50 faces, achieving state‑of‑the‑art geometric fidelity and distributional alignment compared to sequence‑based baselines.
arXiv:2606. 01891v1 Announce Type: cross Abstract: Mid-surface abstraction is essential for finite element analysis of thin-walled CAD models.
arXiv:2606. 26713v1 Announce Type: new Abstract: As semiconductor technology nodes scale, computational lithography is essential for ensuring yield and performance.