LevelSyn is a physical-aware logic synthesis framework that uses a level-asynchronous Graph Neural Network to predict high-fidelity gate coordinates by learning the structural and directional semantics of And-Inverter Graphs. It incorporates a level-aligned subgraph partitioning strategy to manage industrial-scale designs and integrates these spatial insights into a new synthesis engine within the Berkeley ABC framework. Experiments on the EPFL benchmark suite show LevelSyn outperforms state-of-the-art methods, achieving an average power reduction of 6.89%, a timing delay improvement of 27.48%, and a 99.59% reduction in design rule check violations.
By Jingyi Zhou, Zhengyuan Shi, Ziyang Zheng, Qiang Xu
arXiv:2610.09549v1 Announce Type: new
Abstract: And-Inverter Graphs (AIGs) are fundamental representations for logic synthesis and verification in Electronic Design Automation (EDA). As structured re...
By Qifan Zhang, Ruijie Li, Fangzhou Zhang, Qian Ma, Hui Li, Furui Zhan, Yongpeng Wang, Liying Hao, Shikai Guo
arXiv:2608.28188v1 Announce Type: new
Abstract: Circuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical...
By Jingyi Zhou, Zhengyuan Shi, Jiaying Zhu, Ziyang Zheng, Qiang Xu
arXiv:2602. 19330v2 Announce Type: replace Abstract: Graph Neural Networks (GNNs) are increasingly explored for physical design analysis in Electronic Design Automation, particularly for modeling Clock Tree Synthesis behavior such as clock skew and buffering complexity.
By Barsat Khadka, Kawsher Roxy, Md Rubel Ahmed
Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications. While Field-Programmable Gate Arrays (FPGAs) offer a promising substrate for low-latency inference, conventional FPGA accelerators remain arithmetic-centric, using LUTs primarily as building blocks for numerical operators and peripheral logic.
arXiv:2607. 08427v1 Announce Type: cross Abstract: Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications.
By Jiawei Liang, Haotong Qin, Linfeng Du, Xingyu Liu, Shangkun Li, Hui Yu, Michele Magno, Xinyu Chen, Jiang Xu, Wei Zhang
arXiv:2509. 21886v3 Announce Type: replace Abstract: Learning to compute, the ability to model the functional behavior of a circuit graph, is a fundamental challenge for graph representation learning.
By Ziyang Zheng, Jiaying Zhu, Jingyi Zhou, Qiang Xu
arXiv:2504. 03711v2 Announce Type: replace-cross Abstract: Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications.
By Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Yuchao Wu, Yuzhe Ma, Zhiyao Xie
arXiv:2609.36752v1 Announce Type: new
Abstract: Circuit design is a complex and iterative process that requires expertise in electronic engineering. It involves selecting components while meeting per...
By Pasindu Dodampegama, Praveen Wijesinghe, Naveen Basnayake, Keshawa Jayasundara, Tharindu Bandaragoda
The paper introduces STEP‑KD, a Sequential Timing Evaluation via Progressive Knowledge Distillation framework for predicting post‑routing timing from early‑stage design data. By training teacher models at post‑routing, post‑placement, and post‑floorplan stages and sequentially distilling their knowledge to a post‑synthesis student model through representation alignment, STEP‑KD bridges the abstraction gap that hampers existing machine learning approaches. Experiments on diverse circuits show that STEP‑KD reduces the weighted mean absolute percentage error of Total Negative Slack prediction to 19.78% versus 74.84% for the industry‑standard Static Timing Analysis tool.
By Reza Moravej, Fahad Rahman Amik, Zhanguang Zhang, Didier Ch\'etelat, Yingxue Zhang
arXiv:2603. 11075v3 Announce Type: replace-cross Abstract: As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows.
By Runbang Hu, Bo Fang, Bingzhe Li, Yuede Ji
arXiv:2607. 21633v1 Announce Type: new Abstract: Logic Gate Networks (LGNs) implement computation through compositions of Boolean operations, yet unlike classical Boolean circuits, existing LGNs do not reliably benefit from increased depth.
By Taegun An, Dohun kim, Haebeom Lee, Changhee Joo