arXiv Computer Vision

SweepLSD: A One-Pass, O(width)-Memory Line Segment Detector with an Integer-Only Streaming Core and a Real-Time FPGA Realization

arXiv Machine Learning
Sep 25

Albireo: Adaptive, Energy-Efficient Inference Framework for Video Object Detection on the Edge

Albireo is an adaptive, energy‑efficient inference framework for video object detection on edge devices that wraps existing detectors without modification. It uses a 10‑dimensional Kalman filter per active object to decide when to skip detector calls, predicting bounding boxes on skipped frames at near‑zero GPU cost. Evaluated on BDD100K with YOLO and RF‑DETR detectors on NVIDIA Jetson AGX Thor and Orin, Albireo maintains AP@50 within ±1.2 pp of full‑frame inference while reducing energy consumption by 12.1–17.6 % and improving accuracy for some models.

By Amir Taherin, Jos\'e Cano, Bin Ren, Yanzhi Wang, David Kaeli
arXiv Machine Learning
Aug 11

Data collection from highways: a geometric, class-agnostic approach to embedded vehicle counting

arXiv:2608. 07643v1 Announce Type: cross Abstract: Traffic data collection is dominated today by deep object detectors followed by tracking-by-detection, a pipeline that presupposes what is often missing in practice: a detector already trained on the class one wants to count.

By Lucas Gouveia Omena Lopes, William W. M. Lira, Alexandre M. Lima, Thales M. A. Vieira
arXiv Computer Vision
Oct 16

FALCON: FPGA-Accelerated Latency-Certifiable Occupancy Networks for Camera-Based Autonomous Driving

FALCON is a camera‑based 3D occupancy front‑end built on the AMD Kria KR260 FPGA that provides explicit latency guarantees for autonomous driving perception. The system uses cycle‑bounded programmable‑logic compute, a measured inference envelope over 100k frames, and a watchdog to flag stale outputs, achieving all 300k proxy frames within a 100 ms deadline plus at most 10.2 ms. On the full FlashOcc pipeline the board attains 29.88 mIoU on the Occ3D‑nuScenes set, matching 92.8 % of an FP32 baseline, while maintaining tighter tail latency than competing Jetson Orin and datacenter GPUs.

By Haohua Que, Mingkai Liu, Handong Yao
arXiv Computer Vision
Sep 23

NPLSD: Accelerating Line-Segment Detection on NPU Microcontrollers

The paper introduces NPLSD, a pair of line‑segment detectors optimized for the Neural‑ART NPU on STM32N6 microcontrollers. NPLSD‑H retains a convolutional backbone and replaces transformer components with a fully‑convolutional head, while NPLSD‑M adapts a lightweight trunk to the NPU’s supported operators. Trained on ImageNet and ShanghaiTech Wireframe, the models achieve competitive accuracy with 2.63 M and 0.62 M parameters, respectively, and ablation studies show initialization contributes significantly to performance.

By Parsa Hassani Shariat Panahi, Amir Hossein Jalilvand, M. Hassan Najafi
arXiv Computer Vision
Sep 11

Adaptive Dual-Constrained Line Aggregation for Cross-Paradigm Line Segment Detection

The paper introduces Adaptive Dual-Constrained Line Aggregation (ADLA), a framework that extracts line segments across multiple detection paradigms by aggregating pixels from an edge strength map under orientation coherence and bounded orthogonal distance constraints. ADLA dynamically updates line centroids and orientations, incorporates edge strength into various stages, and reduces parameter tuning. Experiments on generic, wireframe, and Manhattan line segment datasets show strong performance, achieving F^H scores of 0.8665, 0.8720, and 0.7297 respectively.

By Chenguang Liu, Chisheng Wang, Huilin Chen, Chuanhua Zhu, Qingquan Li