Validity-Preserving Hierarchical RL for Joint Routing and Switch Placement in EDA
Read the original on arXiv Machine Learning →The Flow has not summarised this story yet — read it at arXiv Machine Learning.
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arXiv:2604. 25191v2 Announce Type: replace-cross Abstract: Chip placement is a critical step in physical design.
arXiv:2609.08232v1 Announce Type: cross Abstract: Detailed routing remains a dominant runtime bottleneck in physical design due to increasing complexity of design rules. Modern routers can struggle t...
The paper introduces a history‑aware offline reinforcement learning policy that predicts iterative cost weights for routing in dense integrated circuit designs. By incorporating a lightweight LSTM and additional router features, the policy retains sequence context and improves convergence across various placement densities and guide qualities. Integrated into any cost‑based router with minimal changes, the approach reduces design rule violations by an average of 92% and cuts runtime by 10%.
arXiv:2606. 08904v1 Announce Type: new Abstract: Macro placement is a fundamental step in modern chip physical design, playing a crucial role in determining the solution quality of high-dimensional combinatorial optimization problems.
Macro placement is a fundamental step in modern chip physical design, playing a crucial role in determining the solution quality of high-dimensional combinatorial optimization problems. Despite recent advancements in machine learning for spatial coordinate determination, the temporal dimension of placement sequencing remains largely governed by static heuristics.
arXiv:2608. 13767v1 Announce Type: new Abstract: Analog IC layout design remains a labor-intensive iterative process dominated by simulation-driven refinement.