arXiv AI
Jun 2
How Can Reinforcement Learning Achieve Expert-level Placement?
arXiv:2604. 25191v2 Announce Type: replace-cross Abstract: Chip placement is a critical step in physical design.
Validity-Preserving Hierarchical RL for Joint Routing and Switch Placement in EDA
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arXiv Machine Learning
Sep 10
Routing Dense Layouts with History-Aware Offline Reinforcement Learning using LSTM
arXiv:2609.08232v1 Announce Type: cross Abstract: Detailed routing remains a dominant runtime bottleneck in physical design due to increasing complexity of design rules. Modern routers can struggle t...
Hugging Face Trending Papers
Sep 8
Routing Dense Layouts with History-Aware Offline Reinforcement Learning using LSTM
The paper introduces a history‑aware offline reinforcement learning policy that predicts iterative cost weights for routing in dense integrated circuit designs. By incorporating a lightweight LSTM and additional router features, the policy retains sequence context and improves convergence across various placement densities and guide qualities. Integrated into any cost‑based router with minimal changes, the approach reduces design rule violations by an average of 92% and cuts runtime by 10%.
arXiv AI
Jun 9
Order Matters: Unveiling the Hidden Impact of Macro Placement Sequences via Proxy-Guided LLM Evolution
arXiv:2606. 08904v1 Announce Type: new Abstract: Macro placement is a fundamental step in modern chip physical design, playing a crucial role in determining the solution quality of high-dimensional combinatorial optimization problems.
Hugging Face Trending Papers
Jun 8
Order Matters: Unveiling the Hidden Impact of Macro Placement Sequences via Proxy-Guided LLM Evolution
Macro placement is a fundamental step in modern chip physical design, playing a crucial role in determining the solution quality of high-dimensional combinatorial optimization problems. Despite recent advancements in machine learning for spatial coordinate determination, the temporal dimension of placement sequencing remains largely governed by static heuristics.
arXiv AI
Aug 17
Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement
arXiv:2608. 13767v1 Announce Type: new Abstract: Analog IC layout design remains a labor-intensive iterative process dominated by simulation-driven refinement.
arXiv Machine Learning
Aug 14
RoutePack: Expert Placement and Attention-Aware Data Packing for MoE Reinforcement Learning
arXiv:2608. 12146v1 Announce Type: cross Abstract: Training Mixture-of-Experts (MoE) models for reinforcement learning (RL) couples two load-balancing problems: sequence composition determines dense attention work in each data-parallel microbatch, while token routing determines sparse expert work on expert-parallel ranks.
arXiv AI
Jun 8
VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification
arXiv:2603. 11075v3 Announce Type: replace-cross Abstract: As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows.
arXiv Computation and Language
Sep 22
Rubric-Guided Process Reward for Stepwise Model Routing
arXiv:2605.29310v2 Announce Type: replace-cross Abstract: Stepwise model routing improves the efficiency of Large Reasoning Models (LRMs) by assigning each reasoning step to a suitable model. Recent...
arXiv Machine Learning
Sep 4
Learning Constraints-Based Adaptive Hypergraph Neural Networks for Solving Vehicle Routing Problems
The paper presents an end‑to‑end framework that uses constraint‑oriented hypergraphs and reinforcement learning to solve vehicle routing problems. It introduces a dynamic hyperedge reconstruction strategy for better hypergraph representation and a double‑pointer attention decoder for iterative solution generation. Experiments on benchmark datasets show that the method removes the need for complex heuristic operators while improving solution quality.
arXiv AI
Sep 4
LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks
LevelSyn is a physical-aware logic synthesis framework that uses a level-asynchronous Graph Neural Network to predict high-fidelity gate coordinates by learning the structural and directional semantics of And-Inverter Graphs. It incorporates a level-aligned subgraph partitioning strategy to manage industrial-scale designs and integrates these spatial insights into a new synthesis engine within the Berkeley ABC framework. Experiments on the EPFL benchmark suite show LevelSyn outperforms state-of-the-art methods, achieving an average power reduction of 6.89%, a timing delay improvement of 27.48%, and a 99.59% reduction in design rule check violations.
arXiv Machine Learning
Aug 5
Beyond Solving: Prescriptive Probing for Neural Routing Solvers
arXiv:2602. 07216v2 Announce Type: replace Abstract: Neural combinatorial optimization (NCO) trains fast heuristics for routing problems, but planners often need more than a single solve: they ask which stop to drop, which transition to preserve, or which subset of stops to remove if a route is infeasible.