arXiv:2508. 16403v3 Announce Type: replace Abstract: Accurately predicting the performance of active radio frequency (RF) circuits is essential for modern wireless systems but remains challenging due to highly nonlinear behavior and the high computational cost of traditional simulation tools.
arXiv:2608. 12687v1 Announce Type: new Abstract: Bayesian optimization (BO) is a sample-efficient framework for analog circuit topology search, where evaluating each candidate topology can require costly simulation.
arXiv:2608. 04999v1 Announce Type: cross Abstract: Analog circuit design automation using reinforcement learning (RL) has emerged as a promising approach for reducing manual effort.
arXiv:2607. 23225v1 Announce Type: new Abstract: As chip manufacturing processes advance to deep submicron nodes, parasitic interconnect effects increasingly dominate the performance of analog and mixed-signal (AMS) circuits and often lead to costly layout iterations.
arXiv:2504. 03711v2 Announce Type: replace-cross Abstract: Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications.
arXiv:2607. 13416v1 Announce Type: new Abstract: Automating analog circuit topology design is essential to reduce the extensive manual effort required to meet increasingly diverse and customized application demands.
arXiv:2609.36752v1 Announce Type: new Abstract: Circuit design is a complex and iterative process that requires expertise in electronic engineering. It involves selecting components while meeting per...
Analog circuit topology synthesis remains challenging because useful designs occupy a tiny fraction of a combinatorial search space, and small structural changes can induce highly nonlinear changes in...
RFChipAgent is a novel multi‑agent flow that uses large language model agents to automate end‑to‑end analog/RF circuit design under human supervision. The system comprises four key components: a retrieval‑augmented generation subsystem that pulls design knowledge from documentation, agents that handle topology selection and schematic/testbench assembly, a hybrid sizing engine that blends TPE and CMA‑ES optimization with simulator feedback, and a trust‑scored simulation database that informs future optimization runs. Validation on GF22FDSOI 60 GHz wideband mm‑wave low‑noise amplifiers demonstrates automated topology generation, specification‑driven exploration, and simulator‑guided optimization, yielding significant reductions in design effort while preserving sign‑off quality.
arXiv:2508. 10409v3 Announce Type: replace-cross Abstract: This paper constructs a textual dataset for training large language models (LLMs) to learn analog circuit knowledge and customizes LLM training techniques.
arXiv:2606. 07463v1 Announce Type: cross Abstract: Pre-layout design space exploration (DSE) for high-speed signal integrity (SI) analysis is often limited by the computational cost of simulations and iterative optimization algorithms within modern electronic design automation (EDA) workflows.
The paper introduces LOADBench, a large open dataset and benchmark suite for machine learning in analog integrated circuit design. It contains over 100 operational amplifier topologies from the SkyWater130 PDK, each with detailed annotations, sizing constraints, testbenches, and thousands of Pareto-optimal sizing-performance pairs generated by NSGA-II. Six standardized benchmark tasks—inverse sizing, topology selection, sub‑circuit classification, structural circuit generation, Pareto‑membership prediction, and multi‑objective optimization—are defined with precise protocols, and all data, annotations, and reference implementations are released under an open license.