arXiv:2607. 13416v1 Announce Type: new Abstract: Automating analog circuit topology design is essential to reduce the extensive manual effort required to meet increasingly diverse and customized application demands.
Summary generated by The Flow from the publisher's feed. The full article lives at arXiv Machine Learning.
arXiv:2608. 13767v1 Announce Type: new Abstract: Analog IC layout design remains a labor-intensive iterative process dominated by simulation-driven refinement.
arXiv:2608. 12687v1 Announce Type: new Abstract: Bayesian optimization (BO) is a sample-efficient framework for analog circuit topology search, where evaluating each candidate topology can require costly simulation.
arXiv:2607. 14165v1 Announce Type: cross Abstract: While Large Language Models (LLMs) have demonstrated significant capability in software code generation, their application to analog Electronic Design Automation (EDA) is bottlenecked.
arXiv:2603. 24714v2 Announce Type: replace Abstract: Analog design often slows down because even small changes to device sizes or biases require expensive simulation cycles, and high-quality solutions typically occupy only a narrow part of a very large search space.
arXiv:2510. 23472v2 Announce Type: replace-cross Abstract: Chip placement is a vital stage in modern chip design, and black-box optimization (BBO) has been applied to it for decades.
arXiv:2607. 14008v1 Announce Type: new Abstract: In this paper, we introduce Lighthouse RL, a sample-efficient reinforcement learning (RL) approach for analog circuit sizing.