arXiv:2607. 15560v1 Announce Type: cross Abstract: Physics-informed neural networks (PINNs) are unusually sensitive to interacting choices of architecture, activation, loss weighting, collocation, optimization, and constraint enforcement.
EvoTreeNAD is a genealogy‑guided evolutionary algorithm that autonomously discovers neural architectures without a predefined seed or search space. Starting from an empty root, it builds a persistent genealogy where each node represents a complete architecture; top‑percentile values from nodes and descendants steer lineage selection. The method combines an Idea Agent that proposes variants and a Code Agent that implements them, with theoretical analysis showing stationary variation regimes and empirical results demonstrating superior performance on CIFAR‑10/100 and MedMNIST‑v2 tasks.
arXiv:2608. 13472v1 Announce Type: cross Abstract: Analog circuit design is a time-consuming, iterative process in a nonlinear and high-dimensional design space that relies heavily on expert intuition.
arXiv:2607. 08791v1 Announce Type: cross Abstract: Designing effective multi-objective Bayesian optimization (MOBO) algorithms requires balancing many interdependent design choices whose optimal configuration is problem-dependent and typically demands deep expertise.
SyntheticHLS is a framework that uses large language models to create large-scale, diverse synthetic high‑level synthesis (HLS) datasets. It employs an iterative, feedback‑guided mutation loop that transforms seed designs into more complex, scalable ones, guided by quantitative metrics of design complexity and scalability. The resulting datasets outperform manually curated or zero‑shot generated ones in training deep learning models for HLS quality‑of‑results, offering broader coverage of design space and better generalization.
arXiv:2608. 12197v1 Announce Type: cross Abstract: Large Language Models (LLMs) are increasingly used in circuit design workflows, yet their reliability on simulator-facing SPICE netlist recognition and manipulation remains poorly understood and is rarely separated from high-level design reasoning.
arXiv:2608. 04999v1 Announce Type: cross Abstract: Analog circuit design automation using reinforcement learning (RL) has emerged as a promising approach for reducing manual effort.
arXiv:2504. 03711v2 Announce Type: replace-cross Abstract: Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications.
arXiv:2607. 13416v1 Announce Type: new Abstract: Automating analog circuit topology design is essential to reduce the extensive manual effort required to meet increasingly diverse and customized application demands.
arXiv:2603. 13092v2 Announce Type: replace Abstract: Yield Multi-Corner Analysis validates circuits across 25+ Process-Voltage-Temperature corners, resulting in a combinatorial simulation cost of $O(K \times N)$ where $K$ denotes corners and $N$ exceeds $10^4$ samples per corner.
arXiv:2603. 09161v2 Announce Type: replace-cross Abstract: Learning effective netlist representations is fundamentally constrained by the scarcity of labeled datasets, as real designs are protected by Intellectual Property (IP) and costly to annotate.
arXiv:2606. 11256v1 Announce Type: cross Abstract: Designing molecules with target properties is most useful when candidate structures are accompanied by feasible synthetic routes.