RFChipAgent is a novel multi‑agent flow that uses large language model agents to automate end‑to‑end analog/RF circuit design under human supervision. The system comprises four key components: a retrieval‑augmented generation subsystem that pulls design knowledge from documentation, agents that handle topology selection and schematic/testbench assembly, a hybrid sizing engine that blends TPE and CMA‑ES optimization with simulator feedback, and a trust‑scored simulation database that informs future optimization runs. Validation on GF22FDSOI 60 GHz wideband mm‑wave low‑noise amplifiers demonstrates automated topology generation, specification‑driven exploration, and simulator‑guided optimization, yielding significant reductions in design effort while preserving sign‑off quality.
Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled technologies. Although rec...
arXiv:2608. 13472v1 Announce Type: cross Abstract: Analog circuit design is a time-consuming, iterative process in a nonlinear and high-dimensional design space that relies heavily on expert intuition.
arXiv:2607. 14165v1 Announce Type: cross Abstract: While Large Language Models (LLMs) have demonstrated significant capability in software code generation, their application to analog Electronic Design Automation (EDA) is bottlenecked.
K-TRAIL is a simulator-guided generative framework that uses diffusion-based layout generation combined with derivative-free ensemble Kalman guidance to design RF and electromagnetic circuits. It allows a black-box EM simulator to refine candidate layouts during generation, supporting synthesis from target S-parameter responses or direct RF performance constraints. Experiments on multi-layer RFIC structures demonstrate improved agreement with target responses and the ability to discover structurally distinct layouts that meet design requirements.
arXiv:2606. 01862v1 Announce Type: cross Abstract: Translating user intents into physical radio signals represents the critical yet notoriously tedious final step in wireless prototyping, as it requires intricate knowledge of physical layer details and presents immense implementation challenges.
arXiv:2608. 13767v1 Announce Type: new Abstract: Analog IC layout design remains a labor-intensive iterative process dominated by simulation-driven refinement.
Agentic Architect is a new framework that uses large language models to automatically evolve and optimize CPU microarchitectural designs. Starting from a seed design, the LLM proposes code changes, which are compiled, simulated, and evaluated against performance, area, and power constraints, with results feeding back into subsequent iterations. The framework was tested on prefetching, cache replacement, and branch prediction, achieving notable speedups and area reductions compared to state‑of‑the‑art designs.
arXiv:2607. 09616v1 Announce Type: cross Abstract: As chip complexity increases and time-to-market pressures grow, front-end design has become a critical bottleneck in chip development.
VortexChat is an agentic framework that autonomously performs end-to-end inverse design of integrated photonic devices from natural language specifications. It combines a large language model decision agent with topology generation, gradient-based refinement, and full-wave electromagnetic simulation in a closed-loop architecture, enabling iterative decomposition of design objectives and minimal human intervention. The system successfully generated devices meeting the Vortex100 Benchmark metrics and fabricated a broadband terahertz perfect vortex beam multiplexer that matched simulation predictions.
The paper introduces TraceDSE, an agentic design space exploration framework for jointly mapping AI inference workloads to heterogeneous edge SoCs and configuring each processing unit. Unlike traditional black-box optimization, TraceDSE uses a proposer‑critic loop powered by large language models and enriched with system execution traces to identify bottlenecks and refine design choices. Experiments on an Intel Meteor Lake SoC show that TraceDSE outperforms state‑of‑the‑art evolutionary and Bayesian methods, improving Pareto frontier hypervolume by up to 68% while reducing hardware evaluations by 6–9×.
arXiv:2610.19508v1 Announce Type: new Abstract: We propose CktHGVAE, a heterogeneous graph variational autoencoder for transistor-level analog/mixedsignal CMOS circuits that takes not only design var...
arXiv:2610.27797v1 Announce Type: new Abstract: 6G will be designed faster than it can be built: AI-driven search already proposes physical-layer algorithms at machine speed, while carrying a single...