The article discusses how large language models (LLMs) are transforming electronic design automation (EDA) by moving beyond isolated task assistance to a hierarchical framework of roles: Generator, Agent, and Orchestrator. It highlights that current LLM-based solutions often produce plausible but not physically correct hardware, suffer from fragmented tools, and lose design context, which hampers scalability to industrial designs. The authors argue for a standardized, physics-aware Orchestrator that integrates tools and agents across the EDA flow to improve reliability and accessibility of hardware design.
By Matthew Youngman, Cristian Sestito, Themis Prodromakis
arXiv:2607. 17528v1 Announce Type: new Abstract: LLM-driven agent systems have emerged as a promising paradigm for electronic design automation (EDA), demonstrating strong potential for automating complex design workflows.
By Jinyuan Deng, Zhengrui Chen, Xufeng Wei, Tianyu Xing, Chenyi Wen, Cheng Zhuo
Large Language Model agents are being explored for chip design, but most methods work directly at RTL. This study compares Direct RTL Design, Agent-based HLS Design, Post-Compiler HLS Refinement, and Post-HLS RTL Refinement, and proposes a combined workflow called Agent-based HLS with RTL Refinement (AHRR). Using FPGAs for evaluation, AHRR achieves a 2.6× geometric‑mean speedup over Direct RTL Design across an 11‑task benchmark suite, demonstrating that higher‑level abstractions and subsequent RTL refinement can improve chip design efficiency.
By Zijian Ding, Yang Zou, Yizhou Sun, Jason Cong
The article reviews the growing use of Large Language Models (LLMs) for generating Verilog code, a key hardware description language in electronic design automation. It surveys 102 papers, covering conferences, journals, and preprints, and addresses four research questions about LLM selection, datasets, techniques, and alignment strategies. The review identifies current limitations and proposes a roadmap for future research in LLM-assisted hardware design.
By Guang Yang, Wei Zheng, Xiang Chen, Dong Liang, Peng Hu, Yukui Yang, Shaohang Peng, Zhenghan Li, Jiahui Feng, Xiao Wei, Kexin Sun, Deyuan Ma, Haotian Cheng, Yiheng Shen, Xing Hu, Terry Yue Zhuo, David Lo
arXiv:2606. 28279v1 Announce Type: cross Abstract: We present HORIZON, a self-evolving agent framework that treats hardware design as repository-level code evolution.
By Cunxi Yu, Chenhui Deng, Nathaniel Pinckney, Brucek Khailany
The paper investigates whether locally deployed large language models can automate hardware design workflows that involve repetitive, dependency-ordered operations using specialized tools. A Model Context Protocol (MCP) server is created to emulate a proprietary hardware design tool, and a benchmark tests single and multi-step edits, invalid requests, misspelled prompts, and multi-server contexts. Seven open-source models are evaluated across different pipeline choices, revealing that strong models can nearly fully cover expected calls, but reliability hinges on task structure and agent configuration, with comprehensive tool descriptions reducing failures and multi-agent setups aiding weaker models at the cost of extra calls.
By Leonardo Liparulo, Francesco Pierri
arXiv:2607. 05174v1 Announce Type: new Abstract: Language agents, i.
By Zhiheng Xi, Dingwen Yang, Jiaqi Liu, Jixuan Huang, Honglin Guo, Baodai Huang, Tinggang Chen, Qi Zhang, Zhonghang Lu, Chenyu Liu, Jiajun Sun, Jiazheng Zhang, Dingwei Zhu, Xin Guo, Junzhe Wang, Zhihao Zhang, Yuming Yang, Junjie Ye, Minghe Gao, Dongrui Liu, Jiaming Ji, Guohao Li, Tao Gui, Qi Zhang, Xuanjing Huang
arXiv:2608. 01791v2 Announce Type: replace-cross Abstract: The rapid development of photonic integrated circuits (PICs) is shifting the design flow from traditional graphical user interface (GUI)-based methods to script-based methods for higher flexibility, portability, and maintainability.
By Xiaohan Jiang, Zeyu Li, Wei Zhang, Jiang Xu
QiMeng-ChipV-RTL is a multi‑agent framework that tackles the challenges of generating Register‑Transfer Level (RTL) code for industrial IP‑level hardware design. By partitioning long design documents into short, localized tasks and using hierarchical planning, localized code generation, interface‑consistent merging, and AST‑guided debugging, it scales to complex specifications. Experiments on the RealBench benchmark show ChipV-RTL achieves a 45.0% pass rate, outperforming state‑of‑the‑art LLMs and agents which reach only 21.6%.
By Hanqi Lyu, Di Huang, Yaoyu Zhu, Kangcheng Liu, Bohan Dou, Chongxiao Li, Pengwei Jin, Shuyao Cheng, Rui Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen
arXiv:2608. 14035v1 Announce Type: new Abstract: Recent developments in large language models (LLMs) and tool-using agents encourage people to explore the potential of using agents in chip design.
By Linyang Li
arXiv:2606. 19387v1 Announce Type: cross Abstract: Large language models (LLMs) have achieved remarkable success in software development.
By You Li, Samuel Mandell, David Z. Pan
arXiv:2606. 13735v1 Announce Type: cross Abstract: Large Language Models (LLM) have shown impressive capabilities in Register Transfer Level (RTL) code generation, particularly for Verilog.
By Yijun Shen, Minghao Shao, Yichen Zhao, Zhuoyan Yu, Boyuan Chen, Yik-Cheung Tam, Muhammad Shafique