arXiv AI

Enhancing Large Language Model-Based Systems for End-to-End Circuit Analysis Problem Solving

The paper introduces an enhanced end‑to‑end circuit analysis framework built on Gemini 2.5 Pro, targeting engineering education. It addresses two key failure modes—circuit‑recognition hallucinations and reasoning‑process hallucinations—by adding a YOLO detector for source polarity re‑identification and an ngspice verification loop for iterative refinement. The resulting pipeline achieves 97.59 % accuracy on 83 undergraduate problems, markedly outperforming the baseline Gemini model and demonstrating significant gains across varied diagram styles and textbooks.

Hugging Face Trending Papers
Jul 2

SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence

Recent advances in Artificial Intelligence (AI) have revolutionized Electronic Design Automation (EDA), particularly through Large Language Models (LLMs) for circuit design tasks. However, their application to analog and mixed-signal domains remains limited by the lack of machine-readable representations of existing circuit design knowledge.

arXiv Machine Learning
Jul 3

SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence

arXiv:2607. 01609v1 Announce Type: new Abstract: Recent advances in Artificial Intelligence (AI) have revolutionized Electronic Design Automation (EDA), particularly through Large Language Models (LLMs) for circuit design tasks.

By Saoud Aldowaish, Yashwanth Karumanchi, Kai-Chen Chiang, Mohammed Ayman Habib, Finn Murphy, Rishen Cao, Morteza Fayazi
arXiv Machine Learning
Oct 22

Sketch2Sim: an end-to-end modular framework for hand-drawn circuit analysis

The paper introduces Sketch2Sim, an end‑to‑end modular framework that transforms hand‑drawn circuit diagrams into SPICE‑compatible netlists and automatically computes nodal voltages and currents. It employs a three‑stage pipeline: dual YOLO detectors for components and text, a CRNN‑CTC OCR module for symbol value extraction, and image‑processing techniques (thresholding, skeletonization, DBSCAN) to identify nodes and map components. Experiments on a curated dataset of 1,000 RLC circuits show robust performance across diverse handwriting styles, lighting, and clutter, and the system includes a user interface for rapid digitization and simulation.

By Mohammad Kawsar, Al Amin Islam Ridoy, Md Rakib Hossain, Farzana Akter, AKM Bahalul Haque, Rejwan Bin Sulaiman, Mohammed Amin Almaiah
arXiv AI
Aug 13

NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation

arXiv:2608. 12197v1 Announce Type: cross Abstract: Large Language Models (LLMs) are increasingly used in circuit design workflows, yet their reliability on simulator-facing SPICE netlist recognition and manipulation remains poorly understood and is rarely separated from high-level design reasoning.

By Jiarui Ma, Jianghan Wang, Yuheng Ma, Ziyi Zhuang, Xiaoguang Liu