arXiv AI
Aug 11
CircuitReason-1k: Benchmarking Long-Horizon Visual-to-Symbolic Reasoning inElectrical Circuits
arXiv:2608. 09374v1 Announce Type: new Abstract: Electrical circuit analysis requires more than recognizing components in an image.
Enhancing Large Language Model-Based Systems for End-to-End Circuit Analysis Problem Solving
The paper introduces an enhanced end‑to‑end circuit analysis framework built on Gemini 2.5 Pro, targeting engineering education. It addresses two key failure modes—circuit‑recognition hallucinations and reasoning‑process hallucinations—by adding a YOLO detector for source polarity re‑identification and an ngspice verification loop for iterative refinement. The resulting pipeline achieves 97.59 % accuracy on 83 undergraduate problems, markedly outperforming the baseline Gemini model and demonstrating significant gains across varied diagram styles and textbooks.
Related stories
Hugging Face Trending Papers
Jul 2
SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence
Recent advances in Artificial Intelligence (AI) have revolutionized Electronic Design Automation (EDA), particularly through Large Language Models (LLMs) for circuit design tasks. However, their application to analog and mixed-signal domains remains limited by the lack of machine-readable representations of existing circuit design knowledge.
arXiv AI
Jul 14
AutoVSR: Automatic Visual-to-Symbolic Reasoning for Symbolic Expression Generation from Circuit Schematic
arXiv:2607. 11338v1 Announce Type: new Abstract: Symbolic expressions can effectively characterize and predict circuit behavior, but deriving them directly from circuit schematics is challenging.
arXiv AI
4d ago
Circuit-MLLM: Topological Logic-Guided Latent-Space Visual Reasoning for Circuit Schematic Understanding
arXiv:2609.15668v1 Announce Type: cross Abstract: Through pre-training on extensive text and image datasets, current multi-modal large language models (MLLMs) achieve strong performance on general ta...
arXiv Machine Learning
Jul 3
SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence
arXiv:2607. 01609v1 Announce Type: new Abstract: Recent advances in Artificial Intelligence (AI) have revolutionized Electronic Design Automation (EDA), particularly through Large Language Models (LLMs) for circuit design tasks.
arXiv AI
Sep 10
CircuTutor: Transforming Static Circuit Problems into Intelligent and Dynamic Tutoring
arXiv:2609.08254v1 Announce Type: new Abstract: Learning direct current circuit concepts requires learners to connect invisible physical quantities, such as current, voltage, resistance, and power, w...
arXiv AI
Aug 13
NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation
arXiv:2608. 12197v1 Announce Type: cross Abstract: Large Language Models (LLMs) are increasingly used in circuit design workflows, yet their reliability on simulator-facing SPICE netlist recognition and manipulation remains poorly understood and is rarely separated from high-level design reasoning.
arXiv AI
Jun 24
Can Language Model Agents be Helpful Circuit Explainers in Mechanistic Interpretability?
arXiv:2606. 24026v1 Announce Type: new Abstract: Mechanistic interpretability has made substantial progress in automatically localizing circuits, but explaining what localized components do remains labor-intensive and difficult to standardize.
arXiv Machine Learning
Jul 22
CircuitKIT : Circuit Discovery, Evaluation, and Application Toolkit for Mechanistic Interpretability
arXiv:2607. 19317v1 Announce Type: new Abstract: Circuit analysis can support not only model explanation but also downstream interventions such as pruning, editing, steering, and selective fine-tuning.
arXiv Machine Learning
Jul 3
A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
arXiv:2504. 03711v2 Announce Type: replace-cross Abstract: Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications.
arXiv Machine Learning
Jun 5
CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
arXiv:2606. 05680v1 Announce Type: cross Abstract: Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design.
arXiv AI
Aug 14
AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models
arXiv:2608. 13472v1 Announce Type: cross Abstract: Analog circuit design is a time-consuming, iterative process in a nonlinear and high-dimensional design space that relies heavily on expert intuition.