The paper introduces VLM-CAD, a workflow that uses Vision Language Models (VLMs) for analog circuit sizing while mitigating spatial blindness and logical hallucinations. It incorporates a neuro‑symbolic parsing module, Image2Net, to convert schematics into topological graphs and JSON, and an Explainable Trust Region Bayesian Optimization method, ExTuRBO, to guide design decisions with sensitivity evidence. Experiments on 12 sizing tasks across six circuits and four technology platforms show a Strict Pass@1 of 23.3% and a Relaxed Pass@1 of 91.7%.
By Guanyuan Pan, Shuai Wang, Yugui Lin, Tiansheng Zhou, Pietro Li\`o, Zhenxin Zhao, Yaqi Wang
arXiv:2608. 09374v1 Announce Type: new Abstract: Electrical circuit analysis requires more than recognizing components in an image.
By Xinqi Yang, Kang An, Tengyue Wang, Zhongyu Yang, Chenxu Du, Yuanchi Zhu, Hebao Zhu, Ziliang Wang, Faqiang Qian, Yunli Yang, Qibing Ren
ReactBench is a benchmark designed to evaluate the structural reasoning abilities of multimodal large language models (MLLMs) using chemical reaction diagrams. The dataset contains 1,618 expert‑annotated question‑answer pairs that test reasoning across four hierarchical task dimensions, from simple endpoint counting to complex topological analysis. Evaluation of 24 MLLMs shows a performance gap of more than 30% between anchor‑based tasks and holistic structural reasoning tasks, indicating that current models struggle with reasoning over branching, converging, and cyclic structures.
By Qiang Xu, Shengyuan Bai, Yu Wang, He Cao, Leqing Chen, Yuanyuan Liu, Bin Feng, Zijing Liu, Yu Li
arXiv:2605.13156v2 Announce Type: replace
Abstract: Vision-language models (VLMs) have demonstrated remarkable capabilities in bridging visual perception and natural language understanding, enabling...
By Jiaxin Liu, Ding Zhong, Yue Wang, Zhidong Yang, Zhaolu Kang, Guangyuan Dong, Qishi Zhan, Pengcheng Fang, Aofan Liu
Recent advances in Artificial Intelligence (AI) have revolutionized Electronic Design Automation (EDA), particularly through Large Language Models (LLMs) for circuit design tasks. However, their application to analog and mixed-signal domains remains limited by the lack of machine-readable representations of existing circuit design knowledge.
arXiv:2610.09549v1 Announce Type: new
Abstract: And-Inverter Graphs (AIGs) are fundamental representations for logic synthesis and verification in Electronic Design Automation (EDA). As structured re...
By Qifan Zhang, Ruijie Li, Fangzhou Zhang, Qian Ma, Hui Li, Furui Zhan, Yongpeng Wang, Liying Hao, Shikai Guo
arXiv:2607. 01609v1 Announce Type: new Abstract: Recent advances in Artificial Intelligence (AI) have revolutionized Electronic Design Automation (EDA), particularly through Large Language Models (LLMs) for circuit design tasks.
By Saoud Aldowaish, Yashwanth Karumanchi, Kai-Chen Chiang, Mohammed Ayman Habib, Finn Murphy, Rishen Cao, Morteza Fayazi
The paper introduces an enhanced end‑to‑end circuit analysis framework built on Gemini 2.5 Pro, targeting engineering education. It addresses two key failure modes—circuit‑recognition hallucinations and reasoning‑process hallucinations—by adding a YOLO detector for source polarity re‑identification and an ngspice verification loop for iterative refinement. The resulting pipeline achieves 97.59 % accuracy on 83 undergraduate problems, markedly outperforming the baseline Gemini model and demonstrating significant gains across varied diagram styles and textbooks.
By Liangliang Chen, Weiyu Sun, Huiru Xie, Yongnuo Cai, Ying Zhang
ReGuLaR introduces a relation‑grounded latent reasoning framework for large vision‑language models, explicitly anchoring latent states to key objects and their inter‑object relations. It employs a training‑time ReGFormer to focus reasoning on question‑relevant visual evidence, while inference proceeds without the ReGFormer. The authors also create the RGROUNDING‑351K dataset and demonstrate that ReGuLaR outperforms existing methods across diverse benchmarks, achieving state‑of‑the‑art results.
By Zihu Wang, Karthik Somayaji N. S, Hejia Geng, Peng Li
arXiv:2608. 13472v1 Announce Type: cross Abstract: Analog circuit design is a time-consuming, iterative process in a nonlinear and high-dimensional design space that relies heavily on expert intuition.
By Mohammed Ayman Habib, Rylan Hart, Morteza Fayazi
arXiv:2607. 11338v1 Announce Type: new Abstract: Symbolic expressions can effectively characterize and predict circuit behavior, but deriving them directly from circuit schematics is challenging.
By Zhe Xiao, Longfei Li, Xu He, Haoying Wu, Zixing Zhang, Mingyu Liu
arXiv:2603. 25629v2 Announce Type: replace-cross Abstract: While language reasoning models excel in many tasks, visual reasoning remains challenging for current large multimodal models (LMMs).
By Andr\'e G. Viveiros, Nuno Gon\c{c}alves, Matthias Lindemann, Andr\'e Martins