arXiv AI

Symbol and Footprint Database for Electronic Components by Agentic Recognition and Generation

arXiv:2607. 19767v1 Announce Type: new Abstract: A rich and recognizable component library is the cornerstone of printed circuit board (PCB) design and generation.

arXiv Computer Vision
Aug 31

PCBnet: A Dataset and Automatic Construction of SPICE Netlists from Schematic Images

PCBnet is a new large‑scale dataset of printed circuit board (PCB) schematics that includes over 300 real‑world designs, more than 50,000 component instances, 150,000 wires, 100,000 text regions, and 400,000 characters, each paired with a SPICE netlist. The authors also introduce an automated pipeline that converts schematic images into netlists, achieving 94.54% component detection mAP, 98.57% text recognition accuracy, and 84.47% end‑to‑end connectivity accuracy. This resource aims to serve as a benchmark and data foundation for future AI‑driven PCB design automation.

By Zhen Huang, Yuhao Gao, Yuzhi Liu, Daian Cheng, Chengyuan Shao, Yucheng Chen, Yongjian Jia, Futing Zhang, Yichen Shi, Wenhao Wang, Zuyan He, Yangbo Wei, Zhanfei Chen, Jinlong Yan, Yu Zhang, Haoying Wu, Ting-Jung Lin, Lei He
arXiv Machine Learning
Jul 3

SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence

arXiv:2607. 01609v1 Announce Type: new Abstract: Recent advances in Artificial Intelligence (AI) have revolutionized Electronic Design Automation (EDA), particularly through Large Language Models (LLMs) for circuit design tasks.

By Saoud Aldowaish, Yashwanth Karumanchi, Kai-Chen Chiang, Mohammed Ayman Habib, Finn Murphy, Rishen Cao, Morteza Fayazi
Hugging Face Trending Papers
Jul 2

SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence

Recent advances in Artificial Intelligence (AI) have revolutionized Electronic Design Automation (EDA), particularly through Large Language Models (LLMs) for circuit design tasks. However, their application to analog and mixed-signal domains remains limited by the lack of machine-readable representations of existing circuit design knowledge.

arXiv Machine Learning
4d ago

THEIA: A Multimodal Dataset and Benchmark for Vision-Language Analysis of Layout

THEIA is a multimodal dataset that pairs thousands of analog circuit layout images with question‑answer conversations, and it introduces a benchmark using a fine‑tuned vision‑language model to analyze GDSII files. The dataset and benchmark enable designers to interact with and query physical layouts as intuitive, meaningful entities. Experiments on five realistic tasks show the fine‑tuned model outperforms general‑purpose vision‑language models by up to 73%, revealing a significant gap between general multimodal reasoning and domain‑specific layout understanding.

By Giuseppe Chiari, Michele Piccoli, Federico Viola, Davide Zoni
arXiv Computation and Language
Sep 4

VisCAD: A Foundation Model Suite with Multimodal Industrial CAD Intelligence

VisCAD is a foundation model suite that tackles AI-assisted computer-aided design for industrial products, covering both part-level and assembly-level generation. Its core component, VisCAD‑M1, is a 27B model trained for part-level design generation and outperforms existing models on PubCADBench and RealCADBench, achieving a part-level score of 0.5540 and reaching 0.5797 when used as a test-time verifier. VisCAD also offers a domain-specific harness that improves complex assembly generation compared to general-purpose harnesses, showing quantitative and qualitative advantages.

By JoyIndustrial VisCAD Team, Linxin Cai, Qiuhe Hong, Zhichao Huang, Guanlin Li, Hongsen Liu, Ziqi Liu, Yichen Long, Luya Wang, Yuchen Wang, Wenxiang Wu, Huimu Yu, Ning Zhang
arXiv AI
Sep 18

VLM-CAD: VLM-Optimized Collaborative Agent Design Workflow for Analog Circuit Sizing

The paper introduces VLM-CAD, a workflow that uses Vision Language Models (VLMs) for analog circuit sizing while mitigating spatial blindness and logical hallucinations. It incorporates a neuro‑symbolic parsing module, Image2Net, to convert schematics into topological graphs and JSON, and an Explainable Trust Region Bayesian Optimization method, ExTuRBO, to guide design decisions with sensitivity evidence. Experiments on 12 sizing tasks across six circuits and four technology platforms show a Strict Pass@1 of 23.3% and a Relaxed Pass@1 of 91.7%.

By Guanyuan Pan, Shuai Wang, Yugui Lin, Tiansheng Zhou, Pietro Li\`o, Zhenxin Zhao, Yaqi Wang