The paper presents a novel multi‑exit computational scheme for TinyML on an ultra‑low‑power GAP9 SoC, adding confidence‑based gating points to a MobileNetV2 CNN for ImageNet‑100. By allowing inference to stop early, the approach cuts average MAC operations by 41 % (from 313 MMAC to 185 MMAC), reduces inference time by 29 % (49 ms to 35 ms), and saves 24 % in energy (2.1 mJ to 1.6 mJ per frame) with only a ~1 % drop in accuracy. Compared to a state‑of‑the‑art adaptive CNN on the same hardware, the method more than doubles computational efficiency, raising MAC/cycle from 8.1 to 17.2.
By Luca Crupi, Lorenzo Lamberti, Alessandro Giusti, Daniele Palossi
The paper introduces a spike‑aware, gradient‑based mixed‑precision quantization framework for Spiking Neural Networks (SNNs), which assigns bit‑widths adaptively using first‑order gradient information. This approach avoids the memory and computational overhead of Hessian‑based methods like HAWQ‑V2 and is evaluated on VGG, ResNet, and Vision Transformer architectures across CIFAR‑10/100, ImageNet, and DVS‑CIFAR‑10 datasets. On ResNet‑34 with ImageNet, the method attains 73.30% accuracy at 4.78× compression, matching HAWQ‑V2 while reducing memory usage by 2.31× and bit‑allocation runtime by 100×, and it demonstrates energy‑efficient deployment without performance loss.
By Rajshekhar Rakshit, Devgokul B. V, Rakshitha Kalkura, Gopalakrishnan Srinivasan
FAME is an FPGA-based platform that evaluates approximate multipliers directly in hardware, eliminating slow CPU/GPU LUT emulation and reducing evaluation time for DNN inference. It also introduces a pattern-guided retraining method that uses multiplier-specific patterns to recover accuracy losses. Experiments on ResNet‑18 and MobileNetV2 over ImageNet show up to 3.47× faster multiplier evaluation and a 65.5% accuracy improvement over prior retraining approaches.
By Rappy Saha, Nima Amirafshar, Jude Haris, Nima Taherinejad, Jos\'e Cano
arXiv:2606. 03940v1 Announce Type: cross Abstract: In robotics systems, vast amounts of visual data are easily captured at high resolution using low-cost, low-power hardware.
By Dan Jacobellis, Neeraja J. Yadwadkar
In recent years, Spiking Neural Networks (SNNs) have gained massive attention as an energy-efficient neural computing paradigm due to their event-driven and sparse computing capability. However, maint...
arXiv:2610.15092v1 Announce Type: cross
Abstract: Quantization plays a crucial role in efficiently deploying deep learning models on resource-constrained devices. Post-training quantization does not...
By Reem Abdel-Salam, Ahmed H. Abdel-Gawad, Amr G. Wassal
arXiv:2608. 12239v1 Announce Type: cross Abstract: Use this plain-text version for the arXiv abstract field: Learned image compression (LIC) models achieve strong rate-distortion performance but are hindered by high computational complexity and encoding-decoding mismatches across heterogeneous hardware platforms.
By Yuefeng Zhang
The paper introduces a holistic framework that jointly optimizes architecture, token, and bit-width for Vision Transformers (ViTs). It uses Neural Architecture Search (AutoFormer) to find compact backbones, token merging (ToMe) to reduce information processing, and fp16 mixed‑precision inference to accelerate operations. Experiments on ImageNet‑1K and a real‑world 3D X‑ray semiconductor defect dataset show over 10× improvements in throughput and reductions in parameters, FLOPs, and energy while preserving accuracy.
By Phat Nguyen, Xue Geng, Kaixin Xu, Wang Zhe, Xulei Yang, Ngai-Man Cheung
arXiv:2608.21764v1 Announce Type: cross
Abstract: Event-based vision has emerged as a promising paradigm for energy-aware artificial intelligence (AI), offering sparse, low-latency visual signals tha...
By Riadul Islam, Joey Mule, Dhandeep Challagundla, Shahmir Rizvi, Sean Carson, Rachit Saini
arXiv:2607. 06600v1 Announce Type: cross Abstract: Line segment detection is a key building block in visual SLAM, 3D reconstruction, and industrial inspection.
By Parsa Hassani Shariat Panahi, Amir Hossein Jalilvand, M. Hassan Najafi
arXiv:2606. 17249v1 Announce Type: cross Abstract: The dominant trajectory of modern machine learning has been to scale up: larger models, larger accelerators, larger memory budgets.
By Emre Can Kizilates
The paper introduces TRACE, a framework that embeds a Vector Quantizer at the post‑attention residual of each Transformer layer, enabling exchanged activations to be encoded as compact codebook indices. During inference, receivers recover key/value representations via table lookup, eliminating downstream computation and allowing communication–computation overlap. A hierarchical codebook further permits runtime bitrate adaptation, and experiments on ViT‑Base and ViViT‑B demonstrate up to 1.89% accuracy gain, 1.27× speedup, and a 22,624× reduction in communication overhead compared to uncompressed inference.
By Muhammad Azlan Qazi, Alexandros Iosifidis, Qi Zhang