arXiv AI

VLCQ: Post-training quantization for deep neural networks using variable length coding

arXiv Machine Learning
Sep 10

Squeeze10-LLM: Squeezing LLMs' Weights by 10 Times via a Staged Mixed-Precision Quantization Method

Squeeze10-LLM is a staged mixed‑precision post‑training quantization framework that reduces 16‑bit LLM weights to an average of 1.6 bits per weight by assigning 80% of weights to 1 bit and 20% to 4 bits. It introduces Post‑Binarization Activation Robustness (PBAR), a weight significance metric that considers activation impact, and Full Information Activation Supervision (FIAS), a strategy that preserves activation information to limit error propagation. Experiments on LLaMA and LLaMA2 demonstrate that Squeeze10‑LLM achieves state‑of‑the‑art performance for sub‑2‑bit weight‑only quantization, raising average accuracy from 43% to 56% on six zero‑shot classification tasks.

By Qingcheng Zhu, Yangyang Ren, Linlin Yang, Yanjing Li, Sheng Xu, Haodong Zhu, Juan Zhang, Runqi Wang, Baochang Zhang
Hugging Face Trending Papers
Aug 12

HAMP-LIC: Hessian-Aware Mixed-Precision Post-Training Quantization for Learned Image Compression

Use this plain-text version for the arXiv abstract field: Learned image compression (LIC) models achieve strong rate-distortion performance but are hindered by high computational complexity and encoding-decoding mismatches across heterogeneous hardware platforms. Uniform fixed-precision quantization alleviates these issues but suffers severe quality degradation at low bit widths because it ignores differences in the quantization sensitivities of individual layers.

arXiv Machine Learning
Oct 5

16-bit Precision of Convolutional Neural Networks on Microcontroller Units for 8-bit Costs

The paper introduces W16A16, a 16‑bit precision quantization method for convolutional neural networks aimed at microcontroller units. On the Armv7E‑M architecture, W16A16 delivers faster inference speeds and lower energy consumption than existing quantization schemes while reducing quantization errors by roughly tenfold compared to 8‑bit approaches. The authors analyze the MCU architecture, explain why 16‑bit operations yield performance gains, and evaluate empirical errors and resource usage across regression and classification tasks.

By Rui Liu, Benjamin Paa{\ss}en