Hybrid ML for Lightweight Pre-Route Delay Estimation in Open-Source IC Design proposes a lightweight machine learning approach that combines a decision tree with linear regression to improve pre-routing delay estimations for the open-source RTL-to-GDSII tool OpenLane. The model reduces error by 80% compared to OpenLane’s estimates and improves performance by 71% even without using OpenLane-specific parameters. It is over 300 times smaller, twice as fast, and offers higher explainability than traditional delay propagation techniques and more complex ML models.
arXiv:2601.14286v2 Announce Type: replace-cross Abstract: Traditional technology mapping suffers from systemic inaccuracies in delay estimation due to its reliance on abstract, technology-agnostic de...
The paper introduces STEP‑KD, a Sequential Timing Evaluation via Progressive Knowledge Distillation framework for predicting post‑routing timing from early‑stage design data. By training teacher models at post‑routing, post‑placement, and post‑floorplan stages and sequentially distilling their knowledge to a post‑synthesis student model through representation alignment, STEP‑KD bridges the abstraction gap that hampers existing machine learning approaches. Experiments on diverse circuits show that STEP‑KD reduces the weighted mean absolute percentage error of Total Negative Slack prediction to 19.78% versus 74.84% for the industry‑standard Static Timing Analysis tool.
arXiv:2608. 13790v1 Announce Type: cross Abstract: Macro placement significantly affects a chip's post-route performance, power, and area (PPA).
The paper introduces LOADBench, a large open dataset and benchmark suite for machine learning in analog integrated circuit design. It contains over 100 operational amplifier topologies from the SkyWater130 PDK, each with detailed annotations, sizing constraints, testbenches, and thousands of Pareto-optimal sizing-performance pairs generated by NSGA-II. Six standardized benchmark tasks—inverse sizing, topology selection, sub‑circuit classification, structural circuit generation, Pareto‑membership prediction, and multi‑objective optimization—are defined with precise protocols, and all data, annotations, and reference implementations are released under an open license.
arXiv:2603. 11075v3 Announce Type: replace-cross Abstract: As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows.
arXiv:2607. 05187v1 Announce Type: new Abstract: As CMOS technology scales into the deep nanometer regime, digital circuit reliability is increasingly threatened by the combined stochastic effects of Bias Temperature Instability (BTI) and Process Variation (PV).
arXiv:2607. 09063v1 Announce Type: new Abstract: Edge devices are increasingly utilized for deploying deep learning applications on embedded systems.
As CMOS technology scales into the deep nanometer regime, digital circuit reliability is increasingly threatened by the combined stochastic effects of Bias Temperature Instability (BTI) and Process Variation (PV). Traditional reliability analysis methods, which rely on computationally intensive simulations or extensive lookup tables, fail to scale efficiently for large designs, creating a critical bottleneck in design space exploration.
arXiv:2606. 04126v1 Announce Type: cross Abstract: We introduce HighTide, an evolving AI-assisted benchmark suite.
arXiv:2607. 15830v1 Announce Type: cross Abstract: Accurate timing prediction at the register-transfer level (RTL) is a longstanding challenge in design automation.
arXiv:2606. 03574v1 Announce Type: cross Abstract: This work proposes a novel solution to predict pulsar timing residuals with limited data, addressing the critical challenge of data scarcity across spin-frequency subgroups of millisecond pulsars in PTA datasets.
arXiv:2606. 07362v1 Announce Type: new Abstract: As scalable inference services become popular, the cold start latency of an inference engine becomes important.