arXiv Machine Learning
GNN-based Path-aware multi-view Circuit Learning for Technology Mapping
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arXiv Machine Learning
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CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphs
arXiv:2610.09549v1 Announce Type: new Abstract: And-Inverter Graphs (AIGs) are fundamental representations for logic synthesis and verification in Electronic Design Automation (EDA). As structured re...
arXiv Machine Learning
Aug 19
Hybrid ML for Lightweight Pre-Route Delay Estimation in Open-Source IC Design
Hybrid ML for Lightweight Pre-Route Delay Estimation in Open-Source IC Design proposes a lightweight machine learning approach that combines a decision tree with linear regression to improve pre-routing delay estimations for the open-source RTL-to-GDSII tool OpenLane. The model reduces error by 80% compared to OpenLane’s estimates and improves performance by 71% even without using OpenLane-specific parameters. It is over 300 times smaller, twice as fast, and offers higher explainability than traditional delay propagation techniques and more complex ML models.
arXiv AI
Jun 17
TRACE: Learning to Compute on Circuit Graphs
arXiv:2509. 21886v3 Announce Type: replace Abstract: Learning to compute, the ability to model the functional behavior of a circuit graph, is a fundamental challenge for graph representation learning.
Hugging Face Trending Papers
Sep 3
LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks
LevelSyn introduces a physical-aware logic synthesis framework that uses a level-asynchronous Graph Neural Network to predict accurate gate coordinates by learning the structural and directional semantics of And-Inverter Graphs. It incorporates a level-aligned subgraph partitioning strategy to handle large designs and integrates these spatial insights into a new synthesis engine within the Berkeley ABC framework. Experiments on the EPFL benchmark suite show significant improvements, with an average power reduction of 6.89%, a timing delay improvement of 27.48%, and a 99.59% reduction in design rule check violations.
arXiv AI
Aug 17
PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization
arXiv:2608. 13790v1 Announce Type: cross Abstract: Macro placement significantly affects a chip's post-route performance, power, and area (PPA).
arXiv Machine Learning
Oct 7
Climbing the Design Ladder: Sequential Knowledge Distillation for Early-Stage Circuit Timing Prediction
The paper introduces STEP‑KD, a Sequential Timing Evaluation via Progressive Knowledge Distillation framework for predicting post‑routing timing from early‑stage design data. By training teacher models at post‑routing, post‑placement, and post‑floorplan stages and sequentially distilling their knowledge to a post‑synthesis student model through representation alignment, STEP‑KD bridges the abstraction gap that hampers existing machine learning approaches. Experiments on diverse circuits show that STEP‑KD reduces the weighted mean absolute percentage error of Total Negative Slack prediction to 19.78% versus 74.84% for the industry‑standard Static Timing Analysis tool.