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arXiv AI

RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm

arXiv:2607. 15830v1 Announce Type: cross Abstract: Accurate timing prediction at the register-transfer level (RTL) is a longstanding challenge in design automation.

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arXiv Machine Learning
Oct 7

Climbing the Design Ladder: Sequential Knowledge Distillation for Early-Stage Circuit Timing Prediction

The paper introduces STEP‑KD, a Sequential Timing Evaluation via Progressive Knowledge Distillation framework for predicting post‑routing timing from early‑stage design data. By training teacher models at post‑routing, post‑placement, and post‑floorplan stages and sequentially distilling their knowledge to a post‑synthesis student model through representation alignment, STEP‑KD bridges the abstraction gap that hampers existing machine learning approaches. Experiments on diverse circuits show that STEP‑KD reduces the weighted mean absolute percentage error of Total Negative Slack prediction to 19.78% versus 74.84% for the industry‑standard Static Timing Analysis tool.

By Reza Moravej, Fahad Rahman Amik, Zhanguang Zhang, Didier Ch\'etelat, Yingxue Zhang
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arXiv AI
Jun 4

StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis

arXiv:2606. 04246v1 Announce Type: new Abstract: Automatic generation of RTL code for digital hardware designs remains challenging due to long-horizon reasoning, multi-step dependencies, and strict correctness constraints in Verilog and VHDL.

By Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi, Ehsan Degan, Vandana Mukherjee
llmsragreinforcement-learningfine-tuningbenchmarks
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arXiv Machine Learning
Jul 28

Benchmarking LLMs for Verilog Design Flows

arXiv:2607. 22759v1 Announce Type: cross Abstract: Large language models (LLMs) show promise in code generation, but their capabilities to produce correct, synthesizable hardware description language (HDL) code still remain to be properly benchmarked.

By Angshuman Chakravertty, Rahul Koshti, Buddhi Prakash Sharma, Vinay Chamola
llmsbenchmarks
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arXiv AI
Aug 20

Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead

The article reviews the growing use of Large Language Models (LLMs) for generating Verilog code, a key hardware description language in electronic design automation. It surveys 102 papers, covering conferences, journals, and preprints, and addresses four research questions about LLM selection, datasets, techniques, and alignment strategies. The review identifies current limitations and proposes a roadmap for future research in LLM-assisted hardware design.

By Guang Yang, Wei Zheng, Xiang Chen, Dong Liang, Peng Hu, Yukui Yang, Shaohang Peng, Zhenghan Li, Jiahui Feng, Xiao Wei, Kexin Sun, Deyuan Ma, Haotian Cheng, Yiheng Shen, Xing Hu, Terry Yue Zhuo, David Lo
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arXiv Machine Learning
Oct 3

SyntheticHLS: Building Diverse Synthetic High-Level Synthesis Datasets using LLMs

SyntheticHLS is a framework that uses large language models to create large-scale, diverse synthetic high‑level synthesis (HLS) datasets. It employs an iterative, feedback‑guided mutation loop that transforms seed designs into more complex, scalable ones, guided by quantitative metrics of design complexity and scalability. The resulting datasets outperform manually curated or zero‑shot generated ones in training deep learning models for HLS quality‑of‑results, offering broader coverage of design space and better generalization.

By Stefan Abi-Karam, Miaoyan Zhou, Callie Hao
llmsbenchmarks
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