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arXiv Machine Learning By Reza Moravej, Fahad Rahman Amik, Zhanguang Zhang, Didier Ch\'etelat, Yingxue Zhang

Climbing the Design Ladder: Sequential Knowledge Distillation for Early-Stage Circuit Timing Prediction

Read the original on arXiv Machine Learning →

The paper introduces STEP‑KD, a Sequential Timing Evaluation via Progressive Knowledge Distillation framework for predicting post‑routing timing from early‑stage design data. By training teacher models at post‑routing, post‑placement, and post‑floorplan stages and sequentially distilling their knowledge to a post‑synthesis student model through representation alignment, STEP‑KD bridges the abstraction gap that hampers existing machine learning approaches. Experiments on diverse circuits show that STEP‑KD reduces the weighted mean absolute percentage error of Total Negative Slack prediction to 19.78% versus 74.84% for the industry‑standard Static Timing Analysis tool.

Machine-generated by The Flow from the publisher's headline and feed description — not written or checked by a human. The full article lives at arXiv Machine Learning.

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