arXiv:2601.14286v2 Announce Type: replace-cross
Abstract: Traditional technology mapping suffers from systemic inaccuracies in delay estimation due to its reliance on abstract, technology-agnostic de...
By Wentao Jiang, Jingxin Wang, Zhang Hu, Zhengyuan Shi, Chengyu Ma, Qiang Xu, Weikang Qian, Zhufei Chu
The paper introduces STEP‑KD, a Sequential Timing Evaluation via Progressive Knowledge Distillation framework for predicting post‑routing timing from early‑stage design data. By training teacher models at post‑routing, post‑placement, and post‑floorplan stages and sequentially distilling their knowledge to a post‑synthesis student model through representation alignment, STEP‑KD bridges the abstraction gap that hampers existing machine learning approaches. Experiments on diverse circuits show that STEP‑KD reduces the weighted mean absolute percentage error of Total Negative Slack prediction to 19.78% versus 74.84% for the industry‑standard Static Timing Analysis tool.
By Reza Moravej, Fahad Rahman Amik, Zhanguang Zhang, Didier Ch\'etelat, Yingxue Zhang
arXiv:2608. 13790v1 Announce Type: cross Abstract: Macro placement significantly affects a chip's post-route performance, power, and area (PPA).
By Ruogu Chen, Jie Han
The paper introduces LOADBench, a large open dataset and benchmark suite for machine learning in analog integrated circuit design. It contains over 100 operational amplifier topologies from the SkyWater130 PDK, each with detailed annotations, sizing constraints, testbenches, and thousands of Pareto-optimal sizing-performance pairs generated by NSGA-II. Six standardized benchmark tasks—inverse sizing, topology selection, sub‑circuit classification, structural circuit generation, Pareto‑membership prediction, and multi‑objective optimization—are defined with precise protocols, and all data, annotations, and reference implementations are released under an open license.
By M. Leibl, F. Azevedo, S. Uhlich, A. Bonetti, A. Venkitaraman, C. Hsieh, P. Pham, L. Servadei, H. Graeb, R. Martins
arXiv:2603. 11075v3 Announce Type: replace-cross Abstract: As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows.
By Runbang Hu, Bo Fang, Bingzhe Li, Yuede Ji
arXiv:2607. 05187v1 Announce Type: new Abstract: As CMOS technology scales into the deep nanometer regime, digital circuit reliability is increasingly threatened by the combined stochastic effects of Bias Temperature Instability (BTI) and Process Variation (PV).
By Arash Esshaghi, Siavash Es'haghi, Gholamreza Shahabadi, Alireza Moradi