Silinx is a free, browser‑based HDL design platform that preserves the familiar Xilinx ISE Project Navigator workflow while eliminating the need to install legacy tools. It supports VHDL, Verilog, C/C++ via HLS, schematic and diagram inputs, and generates HDL automatically. Designs are simulated, built, and programmed onto real Spartan‑3E and Spartan‑6 boards over WebUSB, with an open flow that matches ISE’s bitstreams and even outperforms ISE in resource usage and timing for many designs.
arXiv:2611. 13008v1 Announce Type: cross Abstract: The author describes an open implementation flow, from HDL to a programmable bitstream, for the Xilinx Spartan-3E (XC3S100E to XC3S1200E) and Spartan-6 (XC6SLX16, XC6SLX45), devices that only the discontinued ISE 14.
arXiv:2609.37916v1 Announce Type: cross Abstract: Production machine learning (ML) stacks often split graph compilation and kernel execution across different layers and languages, making backend beha...
arXiv:2608. 06791v1 Announce Type: cross Abstract: Application-specific FPGA accelerators offer substantial performance and energy-efficiency gains across many application domains, but developing them is costly, often requiring months of specialized effort.
Application-specific FPGA accelerators offer substantial performance and energy-efficiency gains across many application domains, but developing them is costly, often requiring months of specialized effort. Even with high-level synthesis (HLS), designers still need extensive hardware expertise to build high-performance accelerators.
FAOPs introduces a formal framework for AI agent workflows, called Functional Agent Operating Procedures, that applies database‑grade discipline to multi‑step agent skills. It normalizes workflows into four progressive normal forms—Decomposed, Typed, Factored, and Scoped—ensuring each atomic step is type‑checked, scoped, bounded, and auditable. The framework includes a provably sound algebra for refactoring and parallelization, extensions for verified termination, optimization, and cost bounds, and an architectural classifier to assess AI necessity, all implemented in the SkillBase system with a runtime executor.
The article reviews the growing use of Large Language Models (LLMs) for generating Verilog code, a key hardware description language in electronic design automation. It surveys 102 papers, covering conferences, journals, and preprints, and addresses four research questions about LLM selection, datasets, techniques, and alignment strategies. The review identifies current limitations and proposes a roadmap for future research in LLM-assisted hardware design.
arXiv:2607. 22759v1 Announce Type: cross Abstract: Large language models (LLMs) show promise in code generation, but their capabilities to produce correct, synthesizable hardware description language (HDL) code still remain to be properly benchmarked.
arXiv:2606. 03895v1 Announce Type: cross Abstract: Large language model (LLM) agents are evolving from request-response assistants into long-running software actors: they maintain state across model calls, fork subtasks, wait for external events, request human authority, generate tools, and perform side effects that must be resumed and audited.
Large language model (LLM) agents are evolving from request-response assistants into long-running software actors: they maintain state across model calls, fork subtasks, wait for external events, request human authority, generate tools, and perform side effects that must be resumed and audited. This paper presents Agent libOS, a library-OS-inspired runtime substrate for LLM agents.
The paper reports on programming AMD XDNA NPUs for the FlashAttention workload using open‑source IRON and MLIR‑AIR compiler tools. It compares four reference designs on XDNA 1 and XDNA 2, showing that a fused kernel that keeps QKᵀ scores in local memory achieves 3.62 TFLOP/s on XDNA 2, doubling throughput and greatly improving energy efficiency over the IRON design and the integrated GPU. Roofline analysis guides when to fuse or stream operators based on each device’s ridge points, and the authors release the reference designs as open source.
arXiv:2602. 07400v2 Announce Type: replace Abstract: Gradient-based LUT- and logic-gate-based neural networks (LUTNet, LogicNets, DiffLogic, PolyLUT, NeuraLUT, WARP-LUT, DWN, LILogicNet, LightLUT) replace multiply-accumulate arithmetic with Boolean lookups.
arXiv:2608.25536v2 Announce Type: replace-cross Abstract: In this work, we propose a view on electronic Neuromorphic Design Automation (eNDA), which we see as a design automation flow that bridges co...