Silinx is a free, browser‑based HDL design platform that preserves the familiar Xilinx ISE Project Navigator workflow while eliminating the need to install legacy tools. It supports VHDL, Verilog, C/C++ via HLS, schematic and diagram inputs, and generates HDL automatically. Designs are simulated, built, and programmed onto real Spartan‑3E and Spartan‑6 boards over WebUSB, with an open flow that matches ISE’s bitstreams and even outperforms ISE in resource usage and timing for many designs.
The paper reports on programming AMD XDNA NPUs for the FlashAttention workload using open‑source IRON and MLIR‑AIR compiler tools. It compares four reference designs on XDNA 1 and XDNA 2, showing that a fused kernel that keeps QKᵀ scores in local memory achieves 3.62 TFLOP/s on XDNA 2, doubling throughput and greatly improving energy efficiency over the IRON design and the integrated GPU. Roofline analysis guides when to fuse or stream operators based on each device’s ridge points, and the authors release the reference designs as open source.
By Erwei Wang, Ephrem Wu, Victor J. B. Jung, Jiajie Li, Andre Rosti, Joseph Melber, Samuel Bayliss
The paper introduces a multi‑shell decoder for Leech‑lattice vector quantization, achieving the best reported 2‑bit quality under its evaluation protocol. It presents a GPU‑friendly layout that fuses dequantization with matrix‑vector multiplication, demonstrating significant speed and memory advantages over traditional one‑hot masks and other 4‑bit methods. Experiments show the new kernel outperforms baseline approaches across multiple model sizes, with measurable gains in throughput and reduced byte traffic.
By Pier-Jean Malandrino (Scub)
The study evaluates the portability of INT8 post‑training quantization across seven hardware platforms, including CPUs, GPUs, and vendor NPUs, by keeping the ONNX model and quantization scales constant. It finds that INT8 performance and output consistency vary significantly: CPU dot‑product instructions determine speedup, identical INT8 outputs only occur when integer kernels match, and vendor NPUs require their own quantization pipelines. The authors also show that edge‑NPU latency is dominated by data transfer rather than compute and provide scripts and reports for reproducibility.
By Yuyeong Shin
arXiv:2608. 08910v1 Announce Type: cross Abstract: PTQTP decomposes LLM weight matrices into two ternary (trit) planes with two free per-group scales.
By Matteo Grella
arXiv:2609.37916v1 Announce Type: cross
Abstract: Production machine learning (ML) stacks often split graph compilation and kernel execution across different layers and languages, making backend beha...
By Eugene Hauptmann, Nataliya Kosmyna