Silinx is a free, browser‑based HDL design platform that preserves the familiar Xilinx ISE Project Navigator workflow while eliminating the need to install legacy tools. It supports VHDL, Verilog, C/C++ via HLS, schematic and diagram inputs, and generates HDL automatically. Designs are simulated, built, and programmed onto real Spartan‑3E and Spartan‑6 boards over WebUSB, with an open flow that matches ISE’s bitstreams and even outperforms ISE in resource usage and timing for many designs.
The paper reports on programming AMD XDNA NPUs for the FlashAttention workload using open‑source IRON and MLIR‑AIR compiler tools. It compares four reference designs on XDNA 1 and XDNA 2, showing that a fused kernel that keeps QKᵀ scores in local memory achieves 3.62 TFLOP/s on XDNA 2, doubling throughput and greatly improving energy efficiency over the IRON design and the integrated GPU. Roofline analysis guides when to fuse or stream operators based on each device’s ridge points, and the authors release the reference designs as open source.
By Erwei Wang, Ephrem Wu, Victor J. B. Jung, Jiajie Li, Andre Rosti, Joseph Melber, Samuel Bayliss
The paper introduces a multi‑shell decoder for Leech‑lattice vector quantization, achieving the best reported 2‑bit quality under its evaluation protocol. It presents a GPU‑friendly layout that fuses dequantization with matrix‑vector multiplication, demonstrating significant speed and memory advantages over traditional one‑hot masks and other 4‑bit methods. Experiments show the new kernel outperforms baseline approaches across multiple model sizes, with measurable gains in throughput and reduced byte traffic.
By Pier-Jean Malandrino (Scub)
The study evaluates the portability of INT8 post‑training quantization across seven hardware platforms, including CPUs, GPUs, and vendor NPUs, by keeping the ONNX model and quantization scales constant. It finds that INT8 performance and output consistency vary significantly: CPU dot‑product instructions determine speedup, identical INT8 outputs only occur when integer kernels match, and vendor NPUs require their own quantization pipelines. The authors also show that edge‑NPU latency is dominated by data transfer rather than compute and provide scripts and reports for reproducibility.
By Yuyeong Shin
arXiv:2608. 08910v1 Announce Type: cross Abstract: PTQTP decomposes LLM weight matrices into two ternary (trit) planes with two free per-group scales.
By Matteo Grella
arXiv:2609.37916v1 Announce Type: cross
Abstract: Production machine learning (ML) stacks often split graph compilation and kernel execution across different layers and languages, making backend beha...
By Eugene Hauptmann, Nataliya Kosmyna
The paper introduces DuoRate, a method for allocating precision in Mixture-of-Experts (MoE) models that separates storage and decoding rates. It stores a uniform tier of weights once and then adapts read precision per workload using a Lagrangian rate‑distortion optimization, reducing the store‑read gap. Experiments on Qwen3-30B-A3B and GSM8K show that DuoRate achieves higher accuracy at lower bit‑per‑weight (bpw) rates compared to fixed‑format baselines.
By Mengqi Guo, Zhe Wei, Yuan Yuan, Jiunn Bin Lim, Boyi Pan, Michael Bi Mi
arXiv:2607. 02630v1 Announce Type: cross Abstract: Hardware accelerators now sit on the critical path of online serving.
By Bojie Li
arXiv:2610. 23796v1 Announce Type: new Abstract: Transformer prefill reuses weights across tokens and is dominated by matrix multiplication and activation data movement; single-token decode has limited reuse and is dominated by weight and KV-cache reads.
By Wei Wang
Prefetch‑Steered Routing (PSR) is a deterministic, cache‑aware method for selecting experts in Mixture‑of‑Experts models that limits physical weight copies to a logical cache of at most *n* experts per layer and token. On several large‑scale models (OLMoE‑1B‑7B, Moonlight‑16B‑A3B, Qwen3.6‑35B‑A3B) PSR achieves 2–2.3× faster decoding than exact routing with LRU and outperforms the Cache‑Prior baseline by 25–30% in many benchmarks, while maintaining comparable accuracy. The approach also shows that speculative block‑level expert selection can be faster than autoregressive decoding when GPU memory is constrained.
By Siming Huang
arXiv:2607. 14618v1 Announce Type: new Abstract: CPUs are the most universal target for on-device LLM inference, but existing low-bit quantization methods offer either coarse operating points or fine-grained mixed precision that is difficult to execute efficiently on CPUs.
By Hyunwoo Oh, Suyeon Jang, Hanning Chen, KyungIn Nam, Sanggeon Yun, Ryozo Masukawa, Mohsen Imani
The paper introduces a system that coordinates heterogeneous accelerators on edge SoCs to run vision–language model inference concurrently, separating a stream’s context from each engine’s key‑value state. By allowing engines to import, reuse, or reconstruct state, the method supports stateful streaming generation and concurrent sequence generation, achieving higher throughput and lower latency than single‑engine baselines. Experiments on Apple M4 Max, Rockchip RK3588, and Qualcomm QCS6490 show significant gains, including up to 27.2% more throughput and 72.7% faster query completion.
By Yilong Li, Chengpo Yan, Yijing Zeng, Hanlei Wu, Mingjun Song, Suman Banerjee