arXiv:2607. 09399v1 Announce Type: cross Abstract: We introduce a novel method for both partial and full optimization of the connections in deep differentiable logic gate networks (LGNs) and lookup table networks (LUTNs).
By Wout Mommen, Lars Keuninckx, Matthias Hartmann, Werner Van Leekwijck, Piet Wambacq
arXiv:2610.01069v1 Announce Type: new
Abstract: Differentiable logic gate networks, which operate using only logic gates, have recently attracted attention as an efficient alternative to conventional...
By Sejin Park, Hongjae Lee, Changwoo Han, Seung-Won Jung
arXiv:2607. 08427v1 Announce Type: cross Abstract: Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications.
By Jiawei Liang, Haotong Qin, Linfeng Du, Xingyu Liu, Shangkun Li, Hui Yu, Michele Magno, Xinyu Chen, Jiang Xu, Wei Zhang
arXiv:2609.13636v1 Announce Type: cross
Abstract: Privacy-preserving inference via Torus Fully Homomorphic Encryption (TFHE) provides strong protection for sensitive data in outsourced deep learning...
By Mahmoud Y. M. Yassin, Mahmoud AbdelHafeez Sayed, Mostafa Taha
Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications. While Field-Programmable Gate Arrays (FPGAs) offer a promising substrate for low-latency inference, conventional FPGA accelerators remain arithmetic-centric, using LUTs primarily as building blocks for numerical operators and peripheral logic.
arXiv:2602. 07400v2 Announce Type: replace Abstract: Gradient-based LUT- and logic-gate-based neural networks (LUTNet, LogicNets, DiffLogic, PolyLUT, NeuraLUT, WARP-LUT, DWN, LILogicNet, LightLUT) replace multiply-accumulate arithmetic with Boolean lookups.
By Simon B\"uhrer, Andreas Plesner, Aczel Till, Roger Wattenhofer