The paper introduces a fully analog readout architecture for vector-matrix multiplication in spiking neural networks that uses voltage-to-time conversion instead of conventional current-mode circuits. By sensing the column voltage directly, the design eliminates the need for current summing and scaling circuitry, thereby reducing area and power consumption. Post-layout simulations of a 10×1 SNN in 130 nm CMOS and tests on a 64×10 digit‑classification network demonstrate the feasibility and efficiency of the proposed approach.
In recent years, driven by the computational demands of data-intensive applications such as artificial intelligence and scientific computing, analog computing has gained renewed interest. Given the diversity of computational tasks and recent advancements in analog CMOS circuits and resistive memory technologies, we refer to the evolving landscape as modern analog computing.
arXiv:2606. 13179v1 Announce Type: cross Abstract: In recent years, driven by the computational demands of data-intensive applications such as artificial intelligence and scientific computing, analog computing has gained renewed interest.
arXiv:2604. 26979v2 Announce Type: replace-cross Abstract: In-memory computing (IMC) is a paradigm that enables neural network inference by computing analog matrix-vector multiplications (MVM) directly in memory crossbar arrays, with the potential for energy efficiency gains over conventional von Neumann architectures.
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arXiv:2606.06159v2 Announce Type: replace-cross Abstract: Spiking neural networks (SNNs) have the potential to emerge as the third generation of neural networks and have attracted increasing attentio...
arXiv:2606. 06159v1 Announce Type: cross Abstract: Spiking neural networks (SNNs) have the potential to emerge as the third generation of neural networks and have attracted increasing attention across a wide range of applications.
arXiv:2605.30361v2 Announce Type: replace-cross Abstract: Spiking Neural Networks (SNNs) offer compelling energy efficiency on neuromorphic hardware, yet their training remains challenging because th...
arXiv:2607. 15123v1 Announce Type: cross Abstract: Recent FPGAs have improved deep learning (DL) inference efficiency through dedicated tensor blocks and in-BRAM computation.
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