arXiv:2505. 14303v3 Announce Type: replace-cross Abstract: Using Resistive Random Access Memory (RRAM) crossbars in Computing-in-Memory (CIM) architectures offers a promising solution to overcome the von Neumann bottleneck.
By Rebecca Pelke, Jos\'e Cubero-Cascante, Nils Bosbach, Niklas Degener, Florian Idrizi, Lennart M. Reimann, Jan Moritz Joseph, Rainer Leupers
arXiv:2606. 02781v1 Announce Type: cross Abstract: Deep neural networks (DNNs) have achieved state-of-the-art performance across diverse domains.
By Sohan Salahuddin Mugdho, Md. Shahedul Hasan, Brahmdutta Dixit, Yang Lv, Jian-Ping Wang, Cheng Wang
arXiv:2606. 00741v1 Announce Type: cross Abstract: Transistor scaling is approaching a quantum-mechanical limit, as thin gate oxides induce electron leakage through quantum tunneling.
By Uiwon Hwang, Jaeho Hwang
The paper introduces a fully analog readout architecture for vector-matrix multiplication in spiking neural networks that uses voltage-to-time conversion instead of conventional current-mode circuits. By sensing the column voltage directly, the design eliminates the need for current summing and scaling circuitry, thereby reducing area and power consumption. Post-layout simulations of a 10×1 SNN in 130 nm CMOS and tests on a 64×10 digit‑classification network demonstrate the feasibility and efficiency of the proposed approach.
By Elia Mateu-Barriendos, \'Alvaro G\'omez-Pau, Josep Rius, Daniel Arum\'i, Rosa Rodr\'iguez-Monta\~n\'es, Salvador Manich
arXiv:2607. 15123v1 Announce Type: cross Abstract: Recent FPGAs have improved deep learning (DL) inference efficiency through dedicated tensor blocks and in-BRAM computation.
By Jiajun Hu, Ruthwik Reddy Sunketa, Lei Zhao, Archit Gajjar, Luca Buonanno, Aman Arora
arXiv:2512.04705v3 Announce Type: replace-cross
Abstract: The deployment of Early-Exiting Neural Networks (EENNs) on edge accelerators requires optimizing not only the network architecture but also i...
By Alaa Zniber, Arne Symons, Ouassim Karrakchou, Marian Verhelst, Mounir Ghogho