arXiv AI
ITP-STDP: A Hardware-Efficient Intrinsic-Timing Power-of-Two Synaptic Learning Engine for On-Chip SNNs
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ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training
arXiv:2606. 06159v1 Announce Type: cross Abstract: Spiking neural networks (SNNs) have the potential to emerge as the third generation of neural networks and have attracted increasing attention across a wide range of applications.
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Hardware-Matched Spiking Neural Networks for Real-Time Purkinje Cell Spike Classification
The paper introduces two compact spiking neural networks for real‑time classification of Purkinje cell spikes on untethered headstages. ConvSNN is mapped to the Matrix Vector Processor of an EFM32PG28 microcontroller, achieving a CS F1 of 0.873 with 1,018 parameters and reducing latency by 62.3% while extending battery life to 33.73 hours. StreamSNN processes one waveform value per timestep on a dedicated SKY130 circuit, reaching a CS F1 of 0.837 with 527 parameters, occupying 0.173 mm² and consuming 0.46 µJ per event with 0.2 ms computation within an 8.3 ms end‑to‑end latency.