arXiv:2611. 13008v1 Announce Type: cross Abstract: The author describes an open implementation flow, from HDL to a programmable bitstream, for the Xilinx Spartan-3E (XC3S100E to XC3S1200E) and Spartan-6 (XC6SLX16, XC6SLX45), devices that only the discontinued ISE 14.
By Pedro Malo
arXiv:2609.37916v1 Announce Type: cross
Abstract: Production machine learning (ML) stacks often split graph compilation and kernel execution across different layers and languages, making backend beha...
By Eugene Hauptmann, Nataliya Kosmyna
arXiv:2608. 06791v1 Announce Type: cross Abstract: Application-specific FPGA accelerators offer substantial performance and energy-efficiency gains across many application domains, but developing them is costly, often requiring months of specialized effort.
By Yuebo Luo, Ahmad Sedigh Baroughi, Philip Stachura, Le Chen, Venkatram Vishwanath, Zhenman Fang, Caiwen Ding
Application-specific FPGA accelerators offer substantial performance and energy-efficiency gains across many application domains, but developing them is costly, often requiring months of specialized effort. Even with high-level synthesis (HLS), designers still need extensive hardware expertise to build high-performance accelerators.
FAOPs introduces a formal framework for AI agent workflows, called Functional Agent Operating Procedures, that applies database‑grade discipline to multi‑step agent skills. It normalizes workflows into four progressive normal forms—Decomposed, Typed, Factored, and Scoped—ensuring each atomic step is type‑checked, scoped, bounded, and auditable. The framework includes a provably sound algebra for refactoring and parallelization, extensions for verified termination, optimization, and cost bounds, and an architectural classifier to assess AI necessity, all implemented in the SkillBase system with a runtime executor.
By Ali Mohammadi Shanghooshabad (JPMorgan Chase,Co.)
The article reviews the growing use of Large Language Models (LLMs) for generating Verilog code, a key hardware description language in electronic design automation. It surveys 102 papers, covering conferences, journals, and preprints, and addresses four research questions about LLM selection, datasets, techniques, and alignment strategies. The review identifies current limitations and proposes a roadmap for future research in LLM-assisted hardware design.
By Guang Yang, Wei Zheng, Xiang Chen, Dong Liang, Peng Hu, Yukui Yang, Shaohang Peng, Zhenghan Li, Jiahui Feng, Xiao Wei, Kexin Sun, Deyuan Ma, Haotian Cheng, Yiheng Shen, Xing Hu, Terry Yue Zhuo, David Lo