The paper introduces NeuroAssertion, a coverage-driven framework for generating RTL assertions that integrates formal trace generation, syntax-guided synthesis, and a two-step large language model (LLM) refinement process. It transforms hard-to-reach control-flow conditions into formal reachability goals, uses model checking to produce diverse traces, and mines initial assertions via SyGuS. The refinement stage employs one LLM to propose candidate assertions for uncovered regions and a second LLM to generate repair grammars that guide symbolic synthesis, resulting in roughly twice as many assertions and higher mutation coverage compared to traditional methods.
By Zhiyuan Yan, Ziyue Zheng, Hongce Zhang
arXiv:2606. 08976v1 Announce Type: new Abstract: LLM-based RTL generation and reasoning is a promising direction for hardware design automation.
By Jing Wang, Shang Liu, Wenji Fang, Yuchao Wu, Yugao Zhu, Zhiyao Xie
arXiv:2606. 19387v1 Announce Type: cross Abstract: Large language models (LLMs) have achieved remarkable success in software development.
By You Li, Samuel Mandell, David Z. Pan
arXiv:2607. 28877v1 Announce Type: cross Abstract: Verification consumes the majority of modern chip design effort, yet the formal verification tools that provide mathematical guarantees of correctness remain expensive and restrictively licensed.
By Ha Trung Tran
arXiv:2606. 05680v1 Announce Type: cross Abstract: Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design.
By Mohammad Akyash, Nowfel Mashnoor, Kimia Azar, Hadi Kamali
arXiv:2606. 15500v1 Announce Type: cross Abstract: Large language models (LLMs) have facilitated impressive progress in software engineering, code generation, tooling, and systems.
By Jing Jin, Robert Chu, Ning Yan, Masood S. Mortazavi