NeuroAbs is a neuro‑symbolic framework designed to accelerate property checking in hardware verification by abstracting RTL designs. It employs large language model (LLM) assisted analysis to select signals for abstraction and combines LLM‑based abstraction with an AST‑based symbolic RTL representation to produce sound abstractions verified via SMT solving. When an abstraction is too coarse, NeuroAbs uses counterexample‑guided refinement (CEGAR) to iteratively improve the model, leading to significant efficiency gains across various verification tasks.
By Zhiyuan Yan, Xiaofeng Zhou, Ziyue Zheng, Ziyi Yang, Wenbin Che, Wei Zhang, Yangdi Lyu, Hongce Zhang
arXiv:2607. 28877v1 Announce Type: cross Abstract: Verification consumes the majority of modern chip design effort, yet the formal verification tools that provide mathematical guarantees of correctness remain expensive and restrictively licensed.
By Ha Trung Tran
arXiv:2608. 02712v1 Announce Type: cross Abstract: Kernel generation for hardware accelerators such as GPUs and NPUs has become a proving ground for large language models (LLMs), and state-of-the-art systems raise correctness through pipelines that couple LLMs with agentic reinforcement learning and evolutionary search.
By Yansong Sun, Shenxiu Wu, Siyuan Chen, Runlin Hou, Junhao Qiu, Junming Cao, Shudi Shao, Zhichao Lu, Qingfu Zhang
arXiv:2606. 08976v1 Announce Type: new Abstract: LLM-based RTL generation and reasoning is a promising direction for hardware design automation.
By Jing Wang, Shang Liu, Wenji Fang, Yuchao Wu, Yugao Zhu, Zhiyao Xie
ProofEvolve is a neuro‑symbolic framework that evolves formally verified symbolic proof structures alongside neural models to expand the knowledge boundary in automated theorem proving. The neural component proposes variation operators such as decompositions, repairs, and schema recombinations, while the Lean kernel verifies every proof transition, ensuring formal soundness. Across three competition‑level Lean benchmarks, ProofEvolve achieves the highest average solve rate among evaluated proof systems.
By Wenqian Ye, Ziwei Guan, Eric Xie, Bohan Liu, Shivani Modi, Buyun Zhang, Ellie Dingqiao Wen, Henry Kautz, Aidong Zhang
arXiv:2607. 26181v1 Announce Type: new Abstract: Functional verification dominates integrated circuit (IC) front-end engineering effort, and a single missed bug that escapes to silicon can trigger a costly respin.
By Xin Xin, Jincheng Lou, Junhui Li, Jinglin Yan, Panda Xiao, Di Wu, Haixiao Li, Weicong Lu, Weijian Fan, Xinyu Qu, Yuxiang Zhao, Min Yu, Zhixiong Di, Yibo Lin