arXiv AI
Jun 16
LLM4RTL: Tool-Assisted LLM for RTL Generation
arXiv:2606. 15500v1 Announce Type: cross Abstract: Large language models (LLMs) have facilitated impressive progress in software engineering, code generation, tooling, and systems.
RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
arXiv:2606. 08976v1 Announce Type: new Abstract: LLM-based RTL generation and reasoning is a promising direction for hardware design automation.
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arXiv Machine Learning
Jul 28
Benchmarking LLMs for Verilog Design Flows
arXiv:2607. 22759v1 Announce Type: cross Abstract: Large language models (LLMs) show promise in code generation, but their capabilities to produce correct, synthesizable hardware description language (HDL) code still remain to be properly benchmarked.
arXiv AI
Jun 12
Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation
arXiv:2606. 12983v1 Announce Type: new Abstract: Automated testbench generation has become a critical bottleneck in large language model (LLM)-driven Register Transfer Level (RTL) workflows, where large numbers of candidate designs must be verified rapidly and reliably.
arXiv AI
Jun 15
VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluation
arXiv:2606. 13735v1 Announce Type: cross Abstract: Large Language Models (LLM) have shown impressive capabilities in Register Transfer Level (RTL) code generation, particularly for Verilog.
arXiv Machine Learning
Jun 5
CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
arXiv:2606. 05680v1 Announce Type: cross Abstract: Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design.
arXiv AI
Jul 21
CLOSER-Bench: Evaluating Budgeted Cross-Stage Design Closure for Hardware Agents
arXiv:2607. 16632v1 Announce Type: cross Abstract: Hardware engineering exposes coding agents to a form of long-horizon work that is difficult to capture with pass-at-k: progress is continuous, tool feedback is delayed and heterogeneous, and a backend failure may require revising RTL rather than tuning another physical-design parameter.
arXiv AI
Jun 19
How LLMs Fail and Generalize in RTL Coding for Hardware Design?
arXiv:2606. 19347v1 Announce Type: cross Abstract: Translating sequential programming priors into the parallel temporal logic of hardware design remains a crucial bottleneck for large language models(LLM).
arXiv AI
Jun 10
EstRTL: Functional Estimation Guided RTL Code Generation
arXiv:2606. 09867v1 Announce Type: cross Abstract: Optimizing register transfer level (RTL) code is of vital importance in hardware design.
arXiv AI
Jul 2
LLVM-Bench: Benchmarking and Advancing Large Language Models for LLVM Compiler Issue Resolution
arXiv:2607. 00700v1 Announce Type: cross Abstract: LLVM is a widely used compiler infrastructure whose scale and complexity make issue resolution labor-intensive and challenging.
arXiv AI
Jun 4
StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis
arXiv:2606. 04246v1 Announce Type: new Abstract: Automatic generation of RTL code for digital hardware designs remains challenging due to long-horizon reasoning, multi-step dependencies, and strict correctness constraints in Verilog and VHDL.
arXiv AI
Jun 19
Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement
arXiv:2606. 19387v1 Announce Type: cross Abstract: Large language models (LLMs) have achieved remarkable success in software development.
arXiv AI
Jul 3
Hawk: Harnessing Hardware-Aware Knowledge for High-Performance NPU Kernel Generation
arXiv:2607. 01590v1 Announce Type: new Abstract: Developing high-performance kernels for Neural Processing Units (NPUs) is a critical industry bottleneck, requiring developers to manually navigate implicit hardware constraints and strict memory hierarchies.