arXiv:2608. 13790v1 Announce Type: cross Abstract: Macro placement significantly affects a chip's post-route performance, power, and area (PPA).
By Ruogu Chen, Jie Han
A new AI-accelerated iterative solver, DAIST, is introduced for 3D-IC thermal modeling. It decomposes a full-package FEM simulation into block-level subdomains, replaces each subdomain solver with a neural operator, and couples them through iterative exchanges of interfacial temperature and heat flux. This approach eliminates the need to retrain models when die count or topology changes and offers a controllable accuracy‑runtime tradeoff, achieving up to 178× speedup with minimal temperature error on tested systems.
By Yixing Li, Jiahang Zhou, Zhiyu Zeng, Xin Ai
arXiv:2607. 07233v1 Announce Type: new Abstract: Deep generative models offer a promising paradigm for topology optimization, enabling rapid design exploration.
By Jinbo Yang, Mingyue Yuan, Boyuan Zhang, Yoshifumi Kitamura, Shikai Jing
arXiv:2607. 17398v1 Announce Type: cross Abstract: Analytical placers rely on differentiable objective functions to guide placement, typically combining intermediate surrogate metrics such as half-perimeter wirelength (HPWL) and cell-density penalties.
By Ruogu Chen, Weihua Xiao, Ramesh Karri, Jie Han
arXiv:2609.21263v1 Announce Type: new
Abstract: Automated macro placement remains a fundamental challenge in VLSI physical design. Despite decades of research, existing approaches predominantly optim...
By Qiufeng Li, Chengxuan Wang, Rongqian Chen, Quan Cheng, Yihui Ren, Chia-Tung Ho, David Z. Pan, Tian Lan, Weidong Cao
arXiv:2604. 23658v2 Announce Type: replace-cross Abstract: Chip placement plays an important role in physical design.
By Peng Xie, Ke Xue, Yunqi Shi, Ruo-Tong Chen, Chengrui Gao, Siyuan Xu, Chenjian Ding, Mingxuan Yuan, Chao Qian