arXiv:2604. 23658v2 Announce Type: replace-cross Abstract: Chip placement plays an important role in physical design.
arXiv:2605. 16451v2 Announce Type: replace-cross Abstract: Macro placement is a pivotal stage in VLSI physical design, fundamentally determining the overall chip performance.
Macro placement is a fundamental step in modern chip physical design, playing a crucial role in determining the solution quality of high-dimensional combinatorial optimization problems. Despite recent advancements in machine learning for spatial coordinate determination, the temporal dimension of placement sequencing remains largely governed by static heuristics.
arXiv:2606. 08904v1 Announce Type: new Abstract: Macro placement is a fundamental step in modern chip physical design, playing a crucial role in determining the solution quality of high-dimensional combinatorial optimization problems.
arXiv:2606. 00228v1 Announce Type: new Abstract: In semiconductor manufacturing, lithography projects circuit layouts onto silicon wafers through an optical mask.
arXiv:2510. 23472v2 Announce Type: replace-cross Abstract: Chip placement is a vital stage in modern chip design, and black-box optimization (BBO) has been applied to it for decades.
arXiv:2608. 13790v1 Announce Type: cross Abstract: Macro placement significantly affects a chip's post-route performance, power, and area (PPA).
arXiv:2604. 25191v2 Announce Type: replace-cross Abstract: Chip placement is a critical step in physical design.
arXiv:2603. 11075v3 Announce Type: replace-cross Abstract: As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows.
arXiv:2606. 07481v1 Announce Type: new Abstract: While Computational Fluid Dynamics (CFD) provides high-fidelity flow fields for optimizing indoor environments, its computational cost limits rapid exploration.
The paper introduces CAT-Flow, a pair of lightweight, training‑free algorithms—CAT‑OV and CAT‑OT—that adapt step‑sizes during Flow Matching inference by estimating curvature in time or state space. These methods avoid extra neural evaluations and achieve constant‑order truncation error bounds. Experiments show that CAT‑OV and CAT‑OT improve image quality metrics across four text‑to‑image Flow Matching models, cutting the required generation steps by up to 40%.
arXiv:2606. 12994v2 Announce Type: replace Abstract: Data-driven engineering design is constrained by the lack of large-scale 3D datasets that pair geometry with physics-based performance labels.
arXiv:2609.00955v1 Announce Type: new Abstract: Diffusion models achieve strong image generation quality but incur high iterative denoising costs. Analog compute-in-memory (CIM) can accelerate matrix...